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      1 //===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the RegisterClassInfo class which provides dynamic
     11 // information about target register classes. Callee saved and reserved
     12 // registers depends on calling conventions and other dynamic information, so
     13 // some things cannot be determined statically.
     14 //
     15 //===----------------------------------------------------------------------===//
     16 
     17 #ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
     18 #define LLVM_CODEGEN_REGISTERCLASSINFO_H
     19 
     20 #include "llvm/ADT/ArrayRef.h"
     21 #include "llvm/ADT/BitVector.h"
     22 #include "llvm/ADT/OwningPtr.h"
     23 #include "llvm/Target/TargetRegisterInfo.h"
     24 
     25 namespace llvm {
     26 
     27 class RegisterClassInfo {
     28   struct RCInfo {
     29     unsigned Tag;
     30     unsigned NumRegs;
     31     bool ProperSubClass;
     32     uint8_t MinCost;
     33     uint16_t LastCostChange;
     34     OwningArrayPtr<MCPhysReg> Order;
     35 
     36     RCInfo()
     37       : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0),
     38         LastCostChange(0) {}
     39 
     40     operator ArrayRef<MCPhysReg>() const {
     41       return makeArrayRef(Order.get(), NumRegs);
     42     }
     43   };
     44 
     45   // Brief cached information for each register class.
     46   OwningArrayPtr<RCInfo> RegClass;
     47 
     48   // Tag changes whenever cached information needs to be recomputed. An RCInfo
     49   // entry is valid when its tag matches.
     50   unsigned Tag;
     51 
     52   const MachineFunction *MF;
     53   const TargetRegisterInfo *TRI;
     54 
     55   // Callee saved registers of last MF. Assumed to be valid until the next
     56   // runOnFunction() call.
     57   const uint16_t *CalleeSaved;
     58 
     59   // Map register number to CalleeSaved index + 1;
     60   SmallVector<uint8_t, 4> CSRNum;
     61 
     62   // Reserved registers in the current MF.
     63   BitVector Reserved;
     64 
     65   OwningArrayPtr<unsigned> PSetLimits;
     66 
     67   // Compute all information about RC.
     68   void compute(const TargetRegisterClass *RC) const;
     69 
     70   // Return an up-to-date RCInfo for RC.
     71   const RCInfo &get(const TargetRegisterClass *RC) const {
     72     const RCInfo &RCI = RegClass[RC->getID()];
     73     if (Tag != RCI.Tag)
     74       compute(RC);
     75     return RCI;
     76   }
     77 
     78 public:
     79   RegisterClassInfo();
     80 
     81   /// runOnFunction - Prepare to answer questions about MF. This must be called
     82   /// before any other methods are used.
     83   void runOnMachineFunction(const MachineFunction &MF);
     84 
     85   /// getNumAllocatableRegs - Returns the number of actually allocatable
     86   /// registers in RC in the current function.
     87   unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
     88     return get(RC).NumRegs;
     89   }
     90 
     91   /// getOrder - Returns the preferred allocation order for RC. The order
     92   /// contains no reserved registers, and registers that alias callee saved
     93   /// registers come last.
     94   ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
     95     return get(RC);
     96   }
     97 
     98   /// isProperSubClass - Returns true if RC has a legal super-class with more
     99   /// allocatable registers.
    100   ///
    101   /// Register classes like GR32_NOSP are not proper sub-classes because %esp
    102   /// is not allocatable.  Similarly, tGPR is not a proper sub-class in Thumb
    103   /// mode because the GPR super-class is not legal.
    104   bool isProperSubClass(const TargetRegisterClass *RC) const {
    105     return get(RC).ProperSubClass;
    106   }
    107 
    108   /// getLastCalleeSavedAlias - Returns the last callee saved register that
    109   /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
    110   unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
    111     assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
    112     if (unsigned N = CSRNum[PhysReg])
    113       return CalleeSaved[N-1];
    114     return 0;
    115   }
    116 
    117   /// Get the minimum register cost in RC's allocation order.
    118   /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all
    119   /// the registers in getOrder(RC).
    120   unsigned getMinCost(const TargetRegisterClass *RC) {
    121     return get(RC).MinCost;
    122   }
    123 
    124   /// Get the position of the last cost change in getOrder(RC).
    125   ///
    126   /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
    127   /// same cost according to TRI->getCostPerUse().
    128   unsigned getLastCostChange(const TargetRegisterClass *RC) {
    129     return get(RC).LastCostChange;
    130   }
    131 
    132   /// Get the register unit limit for the given pressure set index.
    133   ///
    134   /// RegisterClassInfo adjusts this limit for reserved registers.
    135   unsigned getRegPressureSetLimit(unsigned Idx) const {
    136     if (!PSetLimits[Idx])
    137       PSetLimits[Idx] = computePSetLimit(Idx);
    138     return PSetLimits[Idx];
    139   }
    140 
    141 protected:
    142   unsigned computePSetLimit(unsigned Idx) const;
    143 };
    144 } // end namespace llvm
    145 
    146 #endif
    147