1 //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This class prints an AArch64 MCInst to a .s file. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_AARCH64INSTPRINTER_H 15 #define LLVM_AARCH64INSTPRINTER_H 16 17 #include "MCTargetDesc/AArch64MCTargetDesc.h" 18 #include "Utils/AArch64BaseInfo.h" 19 #include "llvm/MC/MCInstPrinter.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 22 namespace llvm { 23 24 class MCOperand; 25 26 class AArch64InstPrinter : public MCInstPrinter { 27 public: 28 AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, 29 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); 30 31 // Autogenerated by tblgen 32 void printInstruction(const MCInst *MI, raw_ostream &O); 33 bool printAliasInstr(const MCInst *MI, raw_ostream &O); 34 static const char *getRegisterName(unsigned RegNo); 35 static const char *getInstructionName(unsigned Opcode); 36 37 void printRegName(raw_ostream &O, unsigned RegNum) const; 38 39 template<unsigned MemSize, unsigned RmSize> 40 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum, 41 raw_ostream &O) { 42 printAddrRegExtendOperand(MI, OpNum, O, MemSize, RmSize); 43 } 44 45 46 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum, 47 raw_ostream &O, unsigned MemSize, 48 unsigned RmSize); 49 50 void printAddSubImmLSL0Operand(const MCInst *MI, 51 unsigned OpNum, raw_ostream &O); 52 void printAddSubImmLSL12Operand(const MCInst *MI, 53 unsigned OpNum, raw_ostream &O); 54 55 void printBareImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 56 57 template<unsigned RegWidth> 58 void printBFILSBOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 59 void printBFIWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 60 void printBFXWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 61 62 63 void printCondCodeOperand(const MCInst *MI, unsigned OpNum, 64 raw_ostream &O); 65 66 void printCRxOperand(const MCInst *MI, unsigned OpNum, 67 raw_ostream &O); 68 69 void printCVTFixedPosOperand(const MCInst *MI, unsigned OpNum, 70 raw_ostream &O); 71 72 void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o); 73 74 void printFPZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o); 75 76 template<int MemScale> 77 void printOffsetUImm12Operand(const MCInst *MI, 78 unsigned OpNum, raw_ostream &o) { 79 printOffsetUImm12Operand(MI, OpNum, o, MemScale); 80 } 81 82 void printOffsetUImm12Operand(const MCInst *MI, unsigned OpNum, 83 raw_ostream &o, int MemScale); 84 85 template<unsigned field_width, unsigned scale> 86 void printLabelOperand(const MCInst *MI, unsigned OpNum, 87 raw_ostream &O); 88 89 template<unsigned RegWidth> 90 void printLogicalImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 91 92 template<typename SomeNamedImmMapper> 93 void printNamedImmOperand(const MCInst *MI, unsigned OpNum, 94 raw_ostream &O) { 95 printNamedImmOperand(SomeNamedImmMapper(), MI, OpNum, O); 96 } 97 98 void printNamedImmOperand(const NamedImmMapper &Mapper, 99 const MCInst *MI, unsigned OpNum, 100 raw_ostream &O); 101 102 void printSysRegOperand(const A64SysReg::SysRegMapper &Mapper, 103 const MCInst *MI, unsigned OpNum, 104 raw_ostream &O); 105 106 void printMRSOperand(const MCInst *MI, unsigned OpNum, 107 raw_ostream &O) { 108 printSysRegOperand(A64SysReg::MRSMapper(), MI, OpNum, O); 109 } 110 111 void printMSROperand(const MCInst *MI, unsigned OpNum, 112 raw_ostream &O) { 113 printSysRegOperand(A64SysReg::MSRMapper(), MI, OpNum, O); 114 } 115 116 void printShiftOperand(const char *name, const MCInst *MI, 117 unsigned OpIdx, raw_ostream &O); 118 119 void printLSLOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 120 121 void printLSROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { 122 printShiftOperand("lsr", MI, OpNum, O); 123 } 124 void printASROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { 125 printShiftOperand("asr", MI, OpNum, O); 126 } 127 void printROROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { 128 printShiftOperand("ror", MI, OpNum, O); 129 } 130 131 template<A64SE::ShiftExtSpecifiers Shift> 132 void printShiftOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { 133 printShiftOperand(MI, OpNum, O, Shift); 134 } 135 136 void printShiftOperand(const MCInst *MI, unsigned OpNum, 137 raw_ostream &O, A64SE::ShiftExtSpecifiers Sh); 138 139 140 void printMoveWideImmOperand(const MCInst *MI, unsigned OpNum, 141 raw_ostream &O); 142 143 template<int MemSize> void 144 printSImm7ScaledOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 145 146 void printOffsetSImm9Operand(const MCInst *MI, unsigned OpNum, 147 raw_ostream &O); 148 149 void printPRFMOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 150 151 template<A64SE::ShiftExtSpecifiers EXT> 152 void printRegExtendOperand(const MCInst *MI, unsigned OpNum, 153 raw_ostream &O) { 154 printRegExtendOperand(MI, OpNum, O, EXT); 155 } 156 157 void printRegExtendOperand(const MCInst *MI, unsigned OpNum, 158 raw_ostream &O, A64SE::ShiftExtSpecifiers Ext); 159 160 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 161 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); 162 163 bool isStackReg(unsigned RegNo) { 164 return RegNo == AArch64::XSP || RegNo == AArch64::WSP; 165 } 166 167 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 168 void printNeonMovImmShiftOperand(const MCInst *MI, unsigned OpNum, 169 raw_ostream &O); 170 void printNeonUImm0Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 171 void printNeonUImm8Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); 172 void printNeonUImm64MaskOperand(const MCInst *MI, unsigned OpNum, 173 raw_ostream &O); 174 }; 175 } 176 177 #endif 178
