1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides basic encoding and assembly information for AArch64. 11 // 12 //===----------------------------------------------------------------------===// 13 #include "AArch64BaseInfo.h" 14 #include "llvm/ADT/APFloat.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringExtras.h" 17 #include "llvm/Support/Regex.h" 18 19 using namespace llvm; 20 21 StringRef NamedImmMapper::toString(uint32_t Value, bool &Valid) const { 22 for (unsigned i = 0; i < NumPairs; ++i) { 23 if (Pairs[i].Value == Value) { 24 Valid = true; 25 return Pairs[i].Name; 26 } 27 } 28 29 Valid = false; 30 return StringRef(); 31 } 32 33 uint32_t NamedImmMapper::fromString(StringRef Name, bool &Valid) const { 34 std::string LowerCaseName = Name.lower(); 35 for (unsigned i = 0; i < NumPairs; ++i) { 36 if (Pairs[i].Name == LowerCaseName) { 37 Valid = true; 38 return Pairs[i].Value; 39 } 40 } 41 42 Valid = false; 43 return -1; 44 } 45 46 bool NamedImmMapper::validImm(uint32_t Value) const { 47 return Value < TooBigImm; 48 } 49 50 const NamedImmMapper::Mapping A64AT::ATMapper::ATPairs[] = { 51 {"s1e1r", S1E1R}, 52 {"s1e2r", S1E2R}, 53 {"s1e3r", S1E3R}, 54 {"s1e1w", S1E1W}, 55 {"s1e2w", S1E2W}, 56 {"s1e3w", S1E3W}, 57 {"s1e0r", S1E0R}, 58 {"s1e0w", S1E0W}, 59 {"s12e1r", S12E1R}, 60 {"s12e1w", S12E1W}, 61 {"s12e0r", S12E0R}, 62 {"s12e0w", S12E0W}, 63 }; 64 65 A64AT::ATMapper::ATMapper() 66 : NamedImmMapper(ATPairs, 0) {} 67 68 const NamedImmMapper::Mapping A64DB::DBarrierMapper::DBarrierPairs[] = { 69 {"oshld", OSHLD}, 70 {"oshst", OSHST}, 71 {"osh", OSH}, 72 {"nshld", NSHLD}, 73 {"nshst", NSHST}, 74 {"nsh", NSH}, 75 {"ishld", ISHLD}, 76 {"ishst", ISHST}, 77 {"ish", ISH}, 78 {"ld", LD}, 79 {"st", ST}, 80 {"sy", SY} 81 }; 82 83 A64DB::DBarrierMapper::DBarrierMapper() 84 : NamedImmMapper(DBarrierPairs, 16u) {} 85 86 const NamedImmMapper::Mapping A64DC::DCMapper::DCPairs[] = { 87 {"zva", ZVA}, 88 {"ivac", IVAC}, 89 {"isw", ISW}, 90 {"cvac", CVAC}, 91 {"csw", CSW}, 92 {"cvau", CVAU}, 93 {"civac", CIVAC}, 94 {"cisw", CISW} 95 }; 96 97 A64DC::DCMapper::DCMapper() 98 : NamedImmMapper(DCPairs, 0) {} 99 100 const NamedImmMapper::Mapping A64IC::ICMapper::ICPairs[] = { 101 {"ialluis", IALLUIS}, 102 {"iallu", IALLU}, 103 {"ivau", IVAU} 104 }; 105 106 A64IC::ICMapper::ICMapper() 107 : NamedImmMapper(ICPairs, 0) {} 108 109 const NamedImmMapper::Mapping A64ISB::ISBMapper::ISBPairs[] = { 110 {"sy", SY}, 111 }; 112 113 A64ISB::ISBMapper::ISBMapper() 114 : NamedImmMapper(ISBPairs, 16) {} 115 116 const NamedImmMapper::Mapping A64PRFM::PRFMMapper::PRFMPairs[] = { 117 {"pldl1keep", PLDL1KEEP}, 118 {"pldl1strm", PLDL1STRM}, 119 {"pldl2keep", PLDL2KEEP}, 120 {"pldl2strm", PLDL2STRM}, 121 {"pldl3keep", PLDL3KEEP}, 122 {"pldl3strm", PLDL3STRM}, 123 {"plil1keep", PLIL1KEEP}, 124 {"plil1strm", PLIL1STRM}, 125 {"plil2keep", PLIL2KEEP}, 126 {"plil2strm", PLIL2STRM}, 127 {"plil3keep", PLIL3KEEP}, 128 {"plil3strm", PLIL3STRM}, 129 {"pstl1keep", PSTL1KEEP}, 130 {"pstl1strm", PSTL1STRM}, 131 {"pstl2keep", PSTL2KEEP}, 132 {"pstl2strm", PSTL2STRM}, 133 {"pstl3keep", PSTL3KEEP}, 134 {"pstl3strm", PSTL3STRM} 135 }; 136 137 A64PRFM::PRFMMapper::PRFMMapper() 138 : NamedImmMapper(PRFMPairs, 32) {} 139 140 const NamedImmMapper::Mapping A64PState::PStateMapper::PStatePairs[] = { 141 {"spsel", SPSel}, 142 {"daifset", DAIFSet}, 143 {"daifclr", DAIFClr} 144 }; 145 146 A64PState::PStateMapper::PStateMapper() 147 : NamedImmMapper(PStatePairs, 0) {} 148 149 const NamedImmMapper::Mapping A64SysReg::MRSMapper::MRSPairs[] = { 150 {"mdccsr_el0", MDCCSR_EL0}, 151 {"dbgdtrrx_el0", DBGDTRRX_EL0}, 152 {"mdrar_el1", MDRAR_EL1}, 153 {"oslsr_el1", OSLSR_EL1}, 154 {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1}, 155 {"pmceid0_el0", PMCEID0_EL0}, 156 {"pmceid1_el0", PMCEID1_EL0}, 157 {"midr_el1", MIDR_EL1}, 158 {"ccsidr_el1", CCSIDR_EL1}, 159 {"clidr_el1", CLIDR_EL1}, 160 {"ctr_el0", CTR_EL0}, 161 {"mpidr_el1", MPIDR_EL1}, 162 {"revidr_el1", REVIDR_EL1}, 163 {"aidr_el1", AIDR_EL1}, 164 {"dczid_el0", DCZID_EL0}, 165 {"id_pfr0_el1", ID_PFR0_EL1}, 166 {"id_pfr1_el1", ID_PFR1_EL1}, 167 {"id_dfr0_el1", ID_DFR0_EL1}, 168 {"id_afr0_el1", ID_AFR0_EL1}, 169 {"id_mmfr0_el1", ID_MMFR0_EL1}, 170 {"id_mmfr1_el1", ID_MMFR1_EL1}, 171 {"id_mmfr2_el1", ID_MMFR2_EL1}, 172 {"id_mmfr3_el1", ID_MMFR3_EL1}, 173 {"id_isar0_el1", ID_ISAR0_EL1}, 174 {"id_isar1_el1", ID_ISAR1_EL1}, 175 {"id_isar2_el1", ID_ISAR2_EL1}, 176 {"id_isar3_el1", ID_ISAR3_EL1}, 177 {"id_isar4_el1", ID_ISAR4_EL1}, 178 {"id_isar5_el1", ID_ISAR5_EL1}, 179 {"id_aa64pfr0_el1", ID_AA64PFR0_EL1}, 180 {"id_aa64pfr1_el1", ID_AA64PFR1_EL1}, 181 {"id_aa64dfr0_el1", ID_AA64DFR0_EL1}, 182 {"id_aa64dfr1_el1", ID_AA64DFR1_EL1}, 183 {"id_aa64afr0_el1", ID_AA64AFR0_EL1}, 184 {"id_aa64afr1_el1", ID_AA64AFR1_EL1}, 185 {"id_aa64isar0_el1", ID_AA64ISAR0_EL1}, 186 {"id_aa64isar1_el1", ID_AA64ISAR1_EL1}, 187 {"id_aa64mmfr0_el1", ID_AA64MMFR0_EL1}, 188 {"id_aa64mmfr1_el1", ID_AA64MMFR1_EL1}, 189 {"mvfr0_el1", MVFR0_EL1}, 190 {"mvfr1_el1", MVFR1_EL1}, 191 {"mvfr2_el1", MVFR2_EL1}, 192 {"rvbar_el1", RVBAR_EL1}, 193 {"rvbar_el2", RVBAR_EL2}, 194 {"rvbar_el3", RVBAR_EL3}, 195 {"isr_el1", ISR_EL1}, 196 {"cntpct_el0", CNTPCT_EL0}, 197 {"cntvct_el0", CNTVCT_EL0}, 198 199 // Trace registers 200 {"trcstatr", TRCSTATR}, 201 {"trcidr8", TRCIDR8}, 202 {"trcidr9", TRCIDR9}, 203 {"trcidr10", TRCIDR10}, 204 {"trcidr11", TRCIDR11}, 205 {"trcidr12", TRCIDR12}, 206 {"trcidr13", TRCIDR13}, 207 {"trcidr0", TRCIDR0}, 208 {"trcidr1", TRCIDR1}, 209 {"trcidr2", TRCIDR2}, 210 {"trcidr3", TRCIDR3}, 211 {"trcidr4", TRCIDR4}, 212 {"trcidr5", TRCIDR5}, 213 {"trcidr6", TRCIDR6}, 214 {"trcidr7", TRCIDR7}, 215 {"trcoslsr", TRCOSLSR}, 216 {"trcpdsr", TRCPDSR}, 217 {"trcdevaff0", TRCDEVAFF0}, 218 {"trcdevaff1", TRCDEVAFF1}, 219 {"trclsr", TRCLSR}, 220 {"trcauthstatus", TRCAUTHSTATUS}, 221 {"trcdevarch", TRCDEVARCH}, 222 {"trcdevid", TRCDEVID}, 223 {"trcdevtype", TRCDEVTYPE}, 224 {"trcpidr4", TRCPIDR4}, 225 {"trcpidr5", TRCPIDR5}, 226 {"trcpidr6", TRCPIDR6}, 227 {"trcpidr7", TRCPIDR7}, 228 {"trcpidr0", TRCPIDR0}, 229 {"trcpidr1", TRCPIDR1}, 230 {"trcpidr2", TRCPIDR2}, 231 {"trcpidr3", TRCPIDR3}, 232 {"trccidr0", TRCCIDR0}, 233 {"trccidr1", TRCCIDR1}, 234 {"trccidr2", TRCCIDR2}, 235 {"trccidr3", TRCCIDR3}, 236 237 // GICv3 registers 238 {"icc_iar1_el1", ICC_IAR1_EL1}, 239 {"icc_iar0_el1", ICC_IAR0_EL1}, 240 {"icc_hppir1_el1", ICC_HPPIR1_EL1}, 241 {"icc_hppir0_el1", ICC_HPPIR0_EL1}, 242 {"icc_rpr_el1", ICC_RPR_EL1}, 243 {"ich_vtr_el2", ICH_VTR_EL2}, 244 {"ich_eisr_el2", ICH_EISR_EL2}, 245 {"ich_elsr_el2", ICH_ELSR_EL2} 246 }; 247 248 A64SysReg::MRSMapper::MRSMapper() { 249 InstPairs = &MRSPairs[0]; 250 NumInstPairs = llvm::array_lengthof(MRSPairs); 251 } 252 253 const NamedImmMapper::Mapping A64SysReg::MSRMapper::MSRPairs[] = { 254 {"dbgdtrtx_el0", DBGDTRTX_EL0}, 255 {"oslar_el1", OSLAR_EL1}, 256 {"pmswinc_el0", PMSWINC_EL0}, 257 258 // Trace registers 259 {"trcoslar", TRCOSLAR}, 260 {"trclar", TRCLAR}, 261 262 // GICv3 registers 263 {"icc_eoir1_el1", ICC_EOIR1_EL1}, 264 {"icc_eoir0_el1", ICC_EOIR0_EL1}, 265 {"icc_dir_el1", ICC_DIR_EL1}, 266 {"icc_sgi1r_el1", ICC_SGI1R_EL1}, 267 {"icc_asgi1r_el1", ICC_ASGI1R_EL1}, 268 {"icc_sgi0r_el1", ICC_SGI0R_EL1} 269 }; 270 271 A64SysReg::MSRMapper::MSRMapper() { 272 InstPairs = &MSRPairs[0]; 273 NumInstPairs = llvm::array_lengthof(MSRPairs); 274 } 275 276 277 const NamedImmMapper::Mapping A64SysReg::SysRegMapper::SysRegPairs[] = { 278 {"osdtrrx_el1", OSDTRRX_EL1}, 279 {"osdtrtx_el1", OSDTRTX_EL1}, 280 {"teecr32_el1", TEECR32_EL1}, 281 {"mdccint_el1", MDCCINT_EL1}, 282 {"mdscr_el1", MDSCR_EL1}, 283 {"dbgdtr_el0", DBGDTR_EL0}, 284 {"oseccr_el1", OSECCR_EL1}, 285 {"dbgvcr32_el2", DBGVCR32_EL2}, 286 {"dbgbvr0_el1", DBGBVR0_EL1}, 287 {"dbgbvr1_el1", DBGBVR1_EL1}, 288 {"dbgbvr2_el1", DBGBVR2_EL1}, 289 {"dbgbvr3_el1", DBGBVR3_EL1}, 290 {"dbgbvr4_el1", DBGBVR4_EL1}, 291 {"dbgbvr5_el1", DBGBVR5_EL1}, 292 {"dbgbvr6_el1", DBGBVR6_EL1}, 293 {"dbgbvr7_el1", DBGBVR7_EL1}, 294 {"dbgbvr8_el1", DBGBVR8_EL1}, 295 {"dbgbvr9_el1", DBGBVR9_EL1}, 296 {"dbgbvr10_el1", DBGBVR10_EL1}, 297 {"dbgbvr11_el1", DBGBVR11_EL1}, 298 {"dbgbvr12_el1", DBGBVR12_EL1}, 299 {"dbgbvr13_el1", DBGBVR13_EL1}, 300 {"dbgbvr14_el1", DBGBVR14_EL1}, 301 {"dbgbvr15_el1", DBGBVR15_EL1}, 302 {"dbgbcr0_el1", DBGBCR0_EL1}, 303 {"dbgbcr1_el1", DBGBCR1_EL1}, 304 {"dbgbcr2_el1", DBGBCR2_EL1}, 305 {"dbgbcr3_el1", DBGBCR3_EL1}, 306 {"dbgbcr4_el1", DBGBCR4_EL1}, 307 {"dbgbcr5_el1", DBGBCR5_EL1}, 308 {"dbgbcr6_el1", DBGBCR6_EL1}, 309 {"dbgbcr7_el1", DBGBCR7_EL1}, 310 {"dbgbcr8_el1", DBGBCR8_EL1}, 311 {"dbgbcr9_el1", DBGBCR9_EL1}, 312 {"dbgbcr10_el1", DBGBCR10_EL1}, 313 {"dbgbcr11_el1", DBGBCR11_EL1}, 314 {"dbgbcr12_el1", DBGBCR12_EL1}, 315 {"dbgbcr13_el1", DBGBCR13_EL1}, 316 {"dbgbcr14_el1", DBGBCR14_EL1}, 317 {"dbgbcr15_el1", DBGBCR15_EL1}, 318 {"dbgwvr0_el1", DBGWVR0_EL1}, 319 {"dbgwvr1_el1", DBGWVR1_EL1}, 320 {"dbgwvr2_el1", DBGWVR2_EL1}, 321 {"dbgwvr3_el1", DBGWVR3_EL1}, 322 {"dbgwvr4_el1", DBGWVR4_EL1}, 323 {"dbgwvr5_el1", DBGWVR5_EL1}, 324 {"dbgwvr6_el1", DBGWVR6_EL1}, 325 {"dbgwvr7_el1", DBGWVR7_EL1}, 326 {"dbgwvr8_el1", DBGWVR8_EL1}, 327 {"dbgwvr9_el1", DBGWVR9_EL1}, 328 {"dbgwvr10_el1", DBGWVR10_EL1}, 329 {"dbgwvr11_el1", DBGWVR11_EL1}, 330 {"dbgwvr12_el1", DBGWVR12_EL1}, 331 {"dbgwvr13_el1", DBGWVR13_EL1}, 332 {"dbgwvr14_el1", DBGWVR14_EL1}, 333 {"dbgwvr15_el1", DBGWVR15_EL1}, 334 {"dbgwcr0_el1", DBGWCR0_EL1}, 335 {"dbgwcr1_el1", DBGWCR1_EL1}, 336 {"dbgwcr2_el1", DBGWCR2_EL1}, 337 {"dbgwcr3_el1", DBGWCR3_EL1}, 338 {"dbgwcr4_el1", DBGWCR4_EL1}, 339 {"dbgwcr5_el1", DBGWCR5_EL1}, 340 {"dbgwcr6_el1", DBGWCR6_EL1}, 341 {"dbgwcr7_el1", DBGWCR7_EL1}, 342 {"dbgwcr8_el1", DBGWCR8_EL1}, 343 {"dbgwcr9_el1", DBGWCR9_EL1}, 344 {"dbgwcr10_el1", DBGWCR10_EL1}, 345 {"dbgwcr11_el1", DBGWCR11_EL1}, 346 {"dbgwcr12_el1", DBGWCR12_EL1}, 347 {"dbgwcr13_el1", DBGWCR13_EL1}, 348 {"dbgwcr14_el1", DBGWCR14_EL1}, 349 {"dbgwcr15_el1", DBGWCR15_EL1}, 350 {"teehbr32_el1", TEEHBR32_EL1}, 351 {"osdlr_el1", OSDLR_EL1}, 352 {"dbgprcr_el1", DBGPRCR_EL1}, 353 {"dbgclaimset_el1", DBGCLAIMSET_EL1}, 354 {"dbgclaimclr_el1", DBGCLAIMCLR_EL1}, 355 {"csselr_el1", CSSELR_EL1}, 356 {"vpidr_el2", VPIDR_EL2}, 357 {"vmpidr_el2", VMPIDR_EL2}, 358 {"sctlr_el1", SCTLR_EL1}, 359 {"sctlr_el2", SCTLR_EL2}, 360 {"sctlr_el3", SCTLR_EL3}, 361 {"actlr_el1", ACTLR_EL1}, 362 {"actlr_el2", ACTLR_EL2}, 363 {"actlr_el3", ACTLR_EL3}, 364 {"cpacr_el1", CPACR_EL1}, 365 {"hcr_el2", HCR_EL2}, 366 {"scr_el3", SCR_EL3}, 367 {"mdcr_el2", MDCR_EL2}, 368 {"sder32_el3", SDER32_EL3}, 369 {"cptr_el2", CPTR_EL2}, 370 {"cptr_el3", CPTR_EL3}, 371 {"hstr_el2", HSTR_EL2}, 372 {"hacr_el2", HACR_EL2}, 373 {"mdcr_el3", MDCR_EL3}, 374 {"ttbr0_el1", TTBR0_EL1}, 375 {"ttbr0_el2", TTBR0_EL2}, 376 {"ttbr0_el3", TTBR0_EL3}, 377 {"ttbr1_el1", TTBR1_EL1}, 378 {"tcr_el1", TCR_EL1}, 379 {"tcr_el2", TCR_EL2}, 380 {"tcr_el3", TCR_EL3}, 381 {"vttbr_el2", VTTBR_EL2}, 382 {"vtcr_el2", VTCR_EL2}, 383 {"dacr32_el2", DACR32_EL2}, 384 {"spsr_el1", SPSR_EL1}, 385 {"spsr_el2", SPSR_EL2}, 386 {"spsr_el3", SPSR_EL3}, 387 {"elr_el1", ELR_EL1}, 388 {"elr_el2", ELR_EL2}, 389 {"elr_el3", ELR_EL3}, 390 {"sp_el0", SP_EL0}, 391 {"sp_el1", SP_EL1}, 392 {"sp_el2", SP_EL2}, 393 {"spsel", SPSel}, 394 {"nzcv", NZCV}, 395 {"daif", DAIF}, 396 {"currentel", CurrentEL}, 397 {"spsr_irq", SPSR_irq}, 398 {"spsr_abt", SPSR_abt}, 399 {"spsr_und", SPSR_und}, 400 {"spsr_fiq", SPSR_fiq}, 401 {"fpcr", FPCR}, 402 {"fpsr", FPSR}, 403 {"dspsr_el0", DSPSR_EL0}, 404 {"dlr_el0", DLR_EL0}, 405 {"ifsr32_el2", IFSR32_EL2}, 406 {"afsr0_el1", AFSR0_EL1}, 407 {"afsr0_el2", AFSR0_EL2}, 408 {"afsr0_el3", AFSR0_EL3}, 409 {"afsr1_el1", AFSR1_EL1}, 410 {"afsr1_el2", AFSR1_EL2}, 411 {"afsr1_el3", AFSR1_EL3}, 412 {"esr_el1", ESR_EL1}, 413 {"esr_el2", ESR_EL2}, 414 {"esr_el3", ESR_EL3}, 415 {"fpexc32_el2", FPEXC32_EL2}, 416 {"far_el1", FAR_EL1}, 417 {"far_el2", FAR_EL2}, 418 {"far_el3", FAR_EL3}, 419 {"hpfar_el2", HPFAR_EL2}, 420 {"par_el1", PAR_EL1}, 421 {"pmcr_el0", PMCR_EL0}, 422 {"pmcntenset_el0", PMCNTENSET_EL0}, 423 {"pmcntenclr_el0", PMCNTENCLR_EL0}, 424 {"pmovsclr_el0", PMOVSCLR_EL0}, 425 {"pmselr_el0", PMSELR_EL0}, 426 {"pmccntr_el0", PMCCNTR_EL0}, 427 {"pmxevtyper_el0", PMXEVTYPER_EL0}, 428 {"pmxevcntr_el0", PMXEVCNTR_EL0}, 429 {"pmuserenr_el0", PMUSERENR_EL0}, 430 {"pmintenset_el1", PMINTENSET_EL1}, 431 {"pmintenclr_el1", PMINTENCLR_EL1}, 432 {"pmovsset_el0", PMOVSSET_EL0}, 433 {"mair_el1", MAIR_EL1}, 434 {"mair_el2", MAIR_EL2}, 435 {"mair_el3", MAIR_EL3}, 436 {"amair_el1", AMAIR_EL1}, 437 {"amair_el2", AMAIR_EL2}, 438 {"amair_el3", AMAIR_EL3}, 439 {"vbar_el1", VBAR_EL1}, 440 {"vbar_el2", VBAR_EL2}, 441 {"vbar_el3", VBAR_EL3}, 442 {"rmr_el1", RMR_EL1}, 443 {"rmr_el2", RMR_EL2}, 444 {"rmr_el3", RMR_EL3}, 445 {"contextidr_el1", CONTEXTIDR_EL1}, 446 {"tpidr_el0", TPIDR_EL0}, 447 {"tpidr_el2", TPIDR_EL2}, 448 {"tpidr_el3", TPIDR_EL3}, 449 {"tpidrro_el0", TPIDRRO_EL0}, 450 {"tpidr_el1", TPIDR_EL1}, 451 {"cntfrq_el0", CNTFRQ_EL0}, 452 {"cntvoff_el2", CNTVOFF_EL2}, 453 {"cntkctl_el1", CNTKCTL_EL1}, 454 {"cnthctl_el2", CNTHCTL_EL2}, 455 {"cntp_tval_el0", CNTP_TVAL_EL0}, 456 {"cnthp_tval_el2", CNTHP_TVAL_EL2}, 457 {"cntps_tval_el1", CNTPS_TVAL_EL1}, 458 {"cntp_ctl_el0", CNTP_CTL_EL0}, 459 {"cnthp_ctl_el2", CNTHP_CTL_EL2}, 460 {"cntps_ctl_el1", CNTPS_CTL_EL1}, 461 {"cntp_cval_el0", CNTP_CVAL_EL0}, 462 {"cnthp_cval_el2", CNTHP_CVAL_EL2}, 463 {"cntps_cval_el1", CNTPS_CVAL_EL1}, 464 {"cntv_tval_el0", CNTV_TVAL_EL0}, 465 {"cntv_ctl_el0", CNTV_CTL_EL0}, 466 {"cntv_cval_el0", CNTV_CVAL_EL0}, 467 {"pmevcntr0_el0", PMEVCNTR0_EL0}, 468 {"pmevcntr1_el0", PMEVCNTR1_EL0}, 469 {"pmevcntr2_el0", PMEVCNTR2_EL0}, 470 {"pmevcntr3_el0", PMEVCNTR3_EL0}, 471 {"pmevcntr4_el0", PMEVCNTR4_EL0}, 472 {"pmevcntr5_el0", PMEVCNTR5_EL0}, 473 {"pmevcntr6_el0", PMEVCNTR6_EL0}, 474 {"pmevcntr7_el0", PMEVCNTR7_EL0}, 475 {"pmevcntr8_el0", PMEVCNTR8_EL0}, 476 {"pmevcntr9_el0", PMEVCNTR9_EL0}, 477 {"pmevcntr10_el0", PMEVCNTR10_EL0}, 478 {"pmevcntr11_el0", PMEVCNTR11_EL0}, 479 {"pmevcntr12_el0", PMEVCNTR12_EL0}, 480 {"pmevcntr13_el0", PMEVCNTR13_EL0}, 481 {"pmevcntr14_el0", PMEVCNTR14_EL0}, 482 {"pmevcntr15_el0", PMEVCNTR15_EL0}, 483 {"pmevcntr16_el0", PMEVCNTR16_EL0}, 484 {"pmevcntr17_el0", PMEVCNTR17_EL0}, 485 {"pmevcntr18_el0", PMEVCNTR18_EL0}, 486 {"pmevcntr19_el0", PMEVCNTR19_EL0}, 487 {"pmevcntr20_el0", PMEVCNTR20_EL0}, 488 {"pmevcntr21_el0", PMEVCNTR21_EL0}, 489 {"pmevcntr22_el0", PMEVCNTR22_EL0}, 490 {"pmevcntr23_el0", PMEVCNTR23_EL0}, 491 {"pmevcntr24_el0", PMEVCNTR24_EL0}, 492 {"pmevcntr25_el0", PMEVCNTR25_EL0}, 493 {"pmevcntr26_el0", PMEVCNTR26_EL0}, 494 {"pmevcntr27_el0", PMEVCNTR27_EL0}, 495 {"pmevcntr28_el0", PMEVCNTR28_EL0}, 496 {"pmevcntr29_el0", PMEVCNTR29_EL0}, 497 {"pmevcntr30_el0", PMEVCNTR30_EL0}, 498 {"pmccfiltr_el0", PMCCFILTR_EL0}, 499 {"pmevtyper0_el0", PMEVTYPER0_EL0}, 500 {"pmevtyper1_el0", PMEVTYPER1_EL0}, 501 {"pmevtyper2_el0", PMEVTYPER2_EL0}, 502 {"pmevtyper3_el0", PMEVTYPER3_EL0}, 503 {"pmevtyper4_el0", PMEVTYPER4_EL0}, 504 {"pmevtyper5_el0", PMEVTYPER5_EL0}, 505 {"pmevtyper6_el0", PMEVTYPER6_EL0}, 506 {"pmevtyper7_el0", PMEVTYPER7_EL0}, 507 {"pmevtyper8_el0", PMEVTYPER8_EL0}, 508 {"pmevtyper9_el0", PMEVTYPER9_EL0}, 509 {"pmevtyper10_el0", PMEVTYPER10_EL0}, 510 {"pmevtyper11_el0", PMEVTYPER11_EL0}, 511 {"pmevtyper12_el0", PMEVTYPER12_EL0}, 512 {"pmevtyper13_el0", PMEVTYPER13_EL0}, 513 {"pmevtyper14_el0", PMEVTYPER14_EL0}, 514 {"pmevtyper15_el0", PMEVTYPER15_EL0}, 515 {"pmevtyper16_el0", PMEVTYPER16_EL0}, 516 {"pmevtyper17_el0", PMEVTYPER17_EL0}, 517 {"pmevtyper18_el0", PMEVTYPER18_EL0}, 518 {"pmevtyper19_el0", PMEVTYPER19_EL0}, 519 {"pmevtyper20_el0", PMEVTYPER20_EL0}, 520 {"pmevtyper21_el0", PMEVTYPER21_EL0}, 521 {"pmevtyper22_el0", PMEVTYPER22_EL0}, 522 {"pmevtyper23_el0", PMEVTYPER23_EL0}, 523 {"pmevtyper24_el0", PMEVTYPER24_EL0}, 524 {"pmevtyper25_el0", PMEVTYPER25_EL0}, 525 {"pmevtyper26_el0", PMEVTYPER26_EL0}, 526 {"pmevtyper27_el0", PMEVTYPER27_EL0}, 527 {"pmevtyper28_el0", PMEVTYPER28_EL0}, 528 {"pmevtyper29_el0", PMEVTYPER29_EL0}, 529 {"pmevtyper30_el0", PMEVTYPER30_EL0}, 530 531 // Trace registers 532 {"trcprgctlr", TRCPRGCTLR}, 533 {"trcprocselr", TRCPROCSELR}, 534 {"trcconfigr", TRCCONFIGR}, 535 {"trcauxctlr", TRCAUXCTLR}, 536 {"trceventctl0r", TRCEVENTCTL0R}, 537 {"trceventctl1r", TRCEVENTCTL1R}, 538 {"trcstallctlr", TRCSTALLCTLR}, 539 {"trctsctlr", TRCTSCTLR}, 540 {"trcsyncpr", TRCSYNCPR}, 541 {"trcccctlr", TRCCCCTLR}, 542 {"trcbbctlr", TRCBBCTLR}, 543 {"trctraceidr", TRCTRACEIDR}, 544 {"trcqctlr", TRCQCTLR}, 545 {"trcvictlr", TRCVICTLR}, 546 {"trcviiectlr", TRCVIIECTLR}, 547 {"trcvissctlr", TRCVISSCTLR}, 548 {"trcvipcssctlr", TRCVIPCSSCTLR}, 549 {"trcvdctlr", TRCVDCTLR}, 550 {"trcvdsacctlr", TRCVDSACCTLR}, 551 {"trcvdarcctlr", TRCVDARCCTLR}, 552 {"trcseqevr0", TRCSEQEVR0}, 553 {"trcseqevr1", TRCSEQEVR1}, 554 {"trcseqevr2", TRCSEQEVR2}, 555 {"trcseqrstevr", TRCSEQRSTEVR}, 556 {"trcseqstr", TRCSEQSTR}, 557 {"trcextinselr", TRCEXTINSELR}, 558 {"trccntrldvr0", TRCCNTRLDVR0}, 559 {"trccntrldvr1", TRCCNTRLDVR1}, 560 {"trccntrldvr2", TRCCNTRLDVR2}, 561 {"trccntrldvr3", TRCCNTRLDVR3}, 562 {"trccntctlr0", TRCCNTCTLR0}, 563 {"trccntctlr1", TRCCNTCTLR1}, 564 {"trccntctlr2", TRCCNTCTLR2}, 565 {"trccntctlr3", TRCCNTCTLR3}, 566 {"trccntvr0", TRCCNTVR0}, 567 {"trccntvr1", TRCCNTVR1}, 568 {"trccntvr2", TRCCNTVR2}, 569 {"trccntvr3", TRCCNTVR3}, 570 {"trcimspec0", TRCIMSPEC0}, 571 {"trcimspec1", TRCIMSPEC1}, 572 {"trcimspec2", TRCIMSPEC2}, 573 {"trcimspec3", TRCIMSPEC3}, 574 {"trcimspec4", TRCIMSPEC4}, 575 {"trcimspec5", TRCIMSPEC5}, 576 {"trcimspec6", TRCIMSPEC6}, 577 {"trcimspec7", TRCIMSPEC7}, 578 {"trcrsctlr2", TRCRSCTLR2}, 579 {"trcrsctlr3", TRCRSCTLR3}, 580 {"trcrsctlr4", TRCRSCTLR4}, 581 {"trcrsctlr5", TRCRSCTLR5}, 582 {"trcrsctlr6", TRCRSCTLR6}, 583 {"trcrsctlr7", TRCRSCTLR7}, 584 {"trcrsctlr8", TRCRSCTLR8}, 585 {"trcrsctlr9", TRCRSCTLR9}, 586 {"trcrsctlr10", TRCRSCTLR10}, 587 {"trcrsctlr11", TRCRSCTLR11}, 588 {"trcrsctlr12", TRCRSCTLR12}, 589 {"trcrsctlr13", TRCRSCTLR13}, 590 {"trcrsctlr14", TRCRSCTLR14}, 591 {"trcrsctlr15", TRCRSCTLR15}, 592 {"trcrsctlr16", TRCRSCTLR16}, 593 {"trcrsctlr17", TRCRSCTLR17}, 594 {"trcrsctlr18", TRCRSCTLR18}, 595 {"trcrsctlr19", TRCRSCTLR19}, 596 {"trcrsctlr20", TRCRSCTLR20}, 597 {"trcrsctlr21", TRCRSCTLR21}, 598 {"trcrsctlr22", TRCRSCTLR22}, 599 {"trcrsctlr23", TRCRSCTLR23}, 600 {"trcrsctlr24", TRCRSCTLR24}, 601 {"trcrsctlr25", TRCRSCTLR25}, 602 {"trcrsctlr26", TRCRSCTLR26}, 603 {"trcrsctlr27", TRCRSCTLR27}, 604 {"trcrsctlr28", TRCRSCTLR28}, 605 {"trcrsctlr29", TRCRSCTLR29}, 606 {"trcrsctlr30", TRCRSCTLR30}, 607 {"trcrsctlr31", TRCRSCTLR31}, 608 {"trcssccr0", TRCSSCCR0}, 609 {"trcssccr1", TRCSSCCR1}, 610 {"trcssccr2", TRCSSCCR2}, 611 {"trcssccr3", TRCSSCCR3}, 612 {"trcssccr4", TRCSSCCR4}, 613 {"trcssccr5", TRCSSCCR5}, 614 {"trcssccr6", TRCSSCCR6}, 615 {"trcssccr7", TRCSSCCR7}, 616 {"trcsscsr0", TRCSSCSR0}, 617 {"trcsscsr1", TRCSSCSR1}, 618 {"trcsscsr2", TRCSSCSR2}, 619 {"trcsscsr3", TRCSSCSR3}, 620 {"trcsscsr4", TRCSSCSR4}, 621 {"trcsscsr5", TRCSSCSR5}, 622 {"trcsscsr6", TRCSSCSR6}, 623 {"trcsscsr7", TRCSSCSR7}, 624 {"trcsspcicr0", TRCSSPCICR0}, 625 {"trcsspcicr1", TRCSSPCICR1}, 626 {"trcsspcicr2", TRCSSPCICR2}, 627 {"trcsspcicr3", TRCSSPCICR3}, 628 {"trcsspcicr4", TRCSSPCICR4}, 629 {"trcsspcicr5", TRCSSPCICR5}, 630 {"trcsspcicr6", TRCSSPCICR6}, 631 {"trcsspcicr7", TRCSSPCICR7}, 632 {"trcpdcr", TRCPDCR}, 633 {"trcacvr0", TRCACVR0}, 634 {"trcacvr1", TRCACVR1}, 635 {"trcacvr2", TRCACVR2}, 636 {"trcacvr3", TRCACVR3}, 637 {"trcacvr4", TRCACVR4}, 638 {"trcacvr5", TRCACVR5}, 639 {"trcacvr6", TRCACVR6}, 640 {"trcacvr7", TRCACVR7}, 641 {"trcacvr8", TRCACVR8}, 642 {"trcacvr9", TRCACVR9}, 643 {"trcacvr10", TRCACVR10}, 644 {"trcacvr11", TRCACVR11}, 645 {"trcacvr12", TRCACVR12}, 646 {"trcacvr13", TRCACVR13}, 647 {"trcacvr14", TRCACVR14}, 648 {"trcacvr15", TRCACVR15}, 649 {"trcacatr0", TRCACATR0}, 650 {"trcacatr1", TRCACATR1}, 651 {"trcacatr2", TRCACATR2}, 652 {"trcacatr3", TRCACATR3}, 653 {"trcacatr4", TRCACATR4}, 654 {"trcacatr5", TRCACATR5}, 655 {"trcacatr6", TRCACATR6}, 656 {"trcacatr7", TRCACATR7}, 657 {"trcacatr8", TRCACATR8}, 658 {"trcacatr9", TRCACATR9}, 659 {"trcacatr10", TRCACATR10}, 660 {"trcacatr11", TRCACATR11}, 661 {"trcacatr12", TRCACATR12}, 662 {"trcacatr13", TRCACATR13}, 663 {"trcacatr14", TRCACATR14}, 664 {"trcacatr15", TRCACATR15}, 665 {"trcdvcvr0", TRCDVCVR0}, 666 {"trcdvcvr1", TRCDVCVR1}, 667 {"trcdvcvr2", TRCDVCVR2}, 668 {"trcdvcvr3", TRCDVCVR3}, 669 {"trcdvcvr4", TRCDVCVR4}, 670 {"trcdvcvr5", TRCDVCVR5}, 671 {"trcdvcvr6", TRCDVCVR6}, 672 {"trcdvcvr7", TRCDVCVR7}, 673 {"trcdvcmr0", TRCDVCMR0}, 674 {"trcdvcmr1", TRCDVCMR1}, 675 {"trcdvcmr2", TRCDVCMR2}, 676 {"trcdvcmr3", TRCDVCMR3}, 677 {"trcdvcmr4", TRCDVCMR4}, 678 {"trcdvcmr5", TRCDVCMR5}, 679 {"trcdvcmr6", TRCDVCMR6}, 680 {"trcdvcmr7", TRCDVCMR7}, 681 {"trccidcvr0", TRCCIDCVR0}, 682 {"trccidcvr1", TRCCIDCVR1}, 683 {"trccidcvr2", TRCCIDCVR2}, 684 {"trccidcvr3", TRCCIDCVR3}, 685 {"trccidcvr4", TRCCIDCVR4}, 686 {"trccidcvr5", TRCCIDCVR5}, 687 {"trccidcvr6", TRCCIDCVR6}, 688 {"trccidcvr7", TRCCIDCVR7}, 689 {"trcvmidcvr0", TRCVMIDCVR0}, 690 {"trcvmidcvr1", TRCVMIDCVR1}, 691 {"trcvmidcvr2", TRCVMIDCVR2}, 692 {"trcvmidcvr3", TRCVMIDCVR3}, 693 {"trcvmidcvr4", TRCVMIDCVR4}, 694 {"trcvmidcvr5", TRCVMIDCVR5}, 695 {"trcvmidcvr6", TRCVMIDCVR6}, 696 {"trcvmidcvr7", TRCVMIDCVR7}, 697 {"trccidcctlr0", TRCCIDCCTLR0}, 698 {"trccidcctlr1", TRCCIDCCTLR1}, 699 {"trcvmidcctlr0", TRCVMIDCCTLR0}, 700 {"trcvmidcctlr1", TRCVMIDCCTLR1}, 701 {"trcitctrl", TRCITCTRL}, 702 {"trcclaimset", TRCCLAIMSET}, 703 {"trcclaimclr", TRCCLAIMCLR}, 704 705 // GICv3 registers 706 {"icc_bpr1_el1", ICC_BPR1_EL1}, 707 {"icc_bpr0_el1", ICC_BPR0_EL1}, 708 {"icc_pmr_el1", ICC_PMR_EL1}, 709 {"icc_ctlr_el1", ICC_CTLR_EL1}, 710 {"icc_ctlr_el3", ICC_CTLR_EL3}, 711 {"icc_sre_el1", ICC_SRE_EL1}, 712 {"icc_sre_el2", ICC_SRE_EL2}, 713 {"icc_sre_el3", ICC_SRE_EL3}, 714 {"icc_igrpen0_el1", ICC_IGRPEN0_EL1}, 715 {"icc_igrpen1_el1", ICC_IGRPEN1_EL1}, 716 {"icc_igrpen1_el3", ICC_IGRPEN1_EL3}, 717 {"icc_seien_el1", ICC_SEIEN_EL1}, 718 {"icc_ap0r0_el1", ICC_AP0R0_EL1}, 719 {"icc_ap0r1_el1", ICC_AP0R1_EL1}, 720 {"icc_ap0r2_el1", ICC_AP0R2_EL1}, 721 {"icc_ap0r3_el1", ICC_AP0R3_EL1}, 722 {"icc_ap1r0_el1", ICC_AP1R0_EL1}, 723 {"icc_ap1r1_el1", ICC_AP1R1_EL1}, 724 {"icc_ap1r2_el1", ICC_AP1R2_EL1}, 725 {"icc_ap1r3_el1", ICC_AP1R3_EL1}, 726 {"ich_ap0r0_el2", ICH_AP0R0_EL2}, 727 {"ich_ap0r1_el2", ICH_AP0R1_EL2}, 728 {"ich_ap0r2_el2", ICH_AP0R2_EL2}, 729 {"ich_ap0r3_el2", ICH_AP0R3_EL2}, 730 {"ich_ap1r0_el2", ICH_AP1R0_EL2}, 731 {"ich_ap1r1_el2", ICH_AP1R1_EL2}, 732 {"ich_ap1r2_el2", ICH_AP1R2_EL2}, 733 {"ich_ap1r3_el2", ICH_AP1R3_EL2}, 734 {"ich_hcr_el2", ICH_HCR_EL2}, 735 {"ich_misr_el2", ICH_MISR_EL2}, 736 {"ich_vmcr_el2", ICH_VMCR_EL2}, 737 {"ich_vseir_el2", ICH_VSEIR_EL2}, 738 {"ich_lr0_el2", ICH_LR0_EL2}, 739 {"ich_lr1_el2", ICH_LR1_EL2}, 740 {"ich_lr2_el2", ICH_LR2_EL2}, 741 {"ich_lr3_el2", ICH_LR3_EL2}, 742 {"ich_lr4_el2", ICH_LR4_EL2}, 743 {"ich_lr5_el2", ICH_LR5_EL2}, 744 {"ich_lr6_el2", ICH_LR6_EL2}, 745 {"ich_lr7_el2", ICH_LR7_EL2}, 746 {"ich_lr8_el2", ICH_LR8_EL2}, 747 {"ich_lr9_el2", ICH_LR9_EL2}, 748 {"ich_lr10_el2", ICH_LR10_EL2}, 749 {"ich_lr11_el2", ICH_LR11_EL2}, 750 {"ich_lr12_el2", ICH_LR12_EL2}, 751 {"ich_lr13_el2", ICH_LR13_EL2}, 752 {"ich_lr14_el2", ICH_LR14_EL2}, 753 {"ich_lr15_el2", ICH_LR15_EL2} 754 }; 755 756 uint32_t 757 A64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const { 758 // First search the registers shared by all 759 std::string NameLower = Name.lower(); 760 for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) { 761 if (SysRegPairs[i].Name == NameLower) { 762 Valid = true; 763 return SysRegPairs[i].Value; 764 } 765 } 766 767 // Now try the instruction-specific registers (either read-only or 768 // write-only). 769 for (unsigned i = 0; i < NumInstPairs; ++i) { 770 if (InstPairs[i].Name == NameLower) { 771 Valid = true; 772 return InstPairs[i].Value; 773 } 774 } 775 776 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits 777 // are: 11 xxx 1x11 xxxx xxx 778 Regex GenericRegPattern("^s3_([0-7])_c(1[15])_c([0-9]|1[0-5])_([0-7])$"); 779 780 SmallVector<StringRef, 4> Ops; 781 if (!GenericRegPattern.match(NameLower, &Ops)) { 782 Valid = false; 783 return -1; 784 } 785 786 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 787 uint32_t Bits; 788 Ops[1].getAsInteger(10, Op1); 789 Ops[2].getAsInteger(10, CRn); 790 Ops[3].getAsInteger(10, CRm); 791 Ops[4].getAsInteger(10, Op2); 792 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 793 794 Valid = true; 795 return Bits; 796 } 797 798 std::string 799 A64SysReg::SysRegMapper::toString(uint32_t Bits, bool &Valid) const { 800 for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) { 801 if (SysRegPairs[i].Value == Bits) { 802 Valid = true; 803 return SysRegPairs[i].Name; 804 } 805 } 806 807 for (unsigned i = 0; i < NumInstPairs; ++i) { 808 if (InstPairs[i].Value == Bits) { 809 Valid = true; 810 return InstPairs[i].Name; 811 } 812 } 813 814 uint32_t Op0 = (Bits >> 14) & 0x3; 815 uint32_t Op1 = (Bits >> 11) & 0x7; 816 uint32_t CRn = (Bits >> 7) & 0xf; 817 uint32_t CRm = (Bits >> 3) & 0xf; 818 uint32_t Op2 = Bits & 0x7; 819 820 // Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic 821 // name. 822 if (Op0 != 3 || (CRn != 11 && CRn != 15)) { 823 Valid = false; 824 return ""; 825 } 826 827 assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg"); 828 829 Valid = true; 830 return "s3_" + utostr(Op1) + "_c" + utostr(CRn) 831 + "_c" + utostr(CRm) + "_" + utostr(Op2); 832 } 833 834 const NamedImmMapper::Mapping A64TLBI::TLBIMapper::TLBIPairs[] = { 835 {"ipas2e1is", IPAS2E1IS}, 836 {"ipas2le1is", IPAS2LE1IS}, 837 {"vmalle1is", VMALLE1IS}, 838 {"alle2is", ALLE2IS}, 839 {"alle3is", ALLE3IS}, 840 {"vae1is", VAE1IS}, 841 {"vae2is", VAE2IS}, 842 {"vae3is", VAE3IS}, 843 {"aside1is", ASIDE1IS}, 844 {"vaae1is", VAAE1IS}, 845 {"alle1is", ALLE1IS}, 846 {"vale1is", VALE1IS}, 847 {"vale2is", VALE2IS}, 848 {"vale3is", VALE3IS}, 849 {"vmalls12e1is", VMALLS12E1IS}, 850 {"vaale1is", VAALE1IS}, 851 {"ipas2e1", IPAS2E1}, 852 {"ipas2le1", IPAS2LE1}, 853 {"vmalle1", VMALLE1}, 854 {"alle2", ALLE2}, 855 {"alle3", ALLE3}, 856 {"vae1", VAE1}, 857 {"vae2", VAE2}, 858 {"vae3", VAE3}, 859 {"aside1", ASIDE1}, 860 {"vaae1", VAAE1}, 861 {"alle1", ALLE1}, 862 {"vale1", VALE1}, 863 {"vale2", VALE2}, 864 {"vale3", VALE3}, 865 {"vmalls12e1", VMALLS12E1}, 866 {"vaale1", VAALE1} 867 }; 868 869 A64TLBI::TLBIMapper::TLBIMapper() 870 : NamedImmMapper(TLBIPairs, 0) {} 871 872 bool A64Imms::isFPImm(const APFloat &Val, uint32_t &Imm8Bits) { 873 const fltSemantics &Sem = Val.getSemantics(); 874 unsigned FracBits = APFloat::semanticsPrecision(Sem) - 1; 875 876 uint32_t ExpMask; 877 switch (FracBits) { 878 case 10: // IEEE half-precision 879 ExpMask = 0x1f; 880 break; 881 case 23: // IEEE single-precision 882 ExpMask = 0xff; 883 break; 884 case 52: // IEEE double-precision 885 ExpMask = 0x7ff; 886 break; 887 case 112: // IEEE quad-precision 888 // No immediates are valid for double precision. 889 return false; 890 default: 891 llvm_unreachable("Only half, single and double precision supported"); 892 } 893 894 uint32_t ExpStart = FracBits; 895 uint64_t FracMask = (1ULL << FracBits) - 1; 896 897 uint32_t Sign = Val.isNegative(); 898 899 uint64_t Bits= Val.bitcastToAPInt().getLimitedValue(); 900 uint64_t Fraction = Bits & FracMask; 901 int32_t Exponent = ((Bits >> ExpStart) & ExpMask); 902 Exponent -= ExpMask >> 1; 903 904 // S[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>, 5):imm8<5:0>:Zeros(19) 905 // D[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>, 8):imm8<5:0>:Zeros(48) 906 // This translates to: only 4 bits of fraction; -3 <= exp <= 4. 907 uint64_t A64FracStart = FracBits - 4; 908 uint64_t A64FracMask = 0xf; 909 910 // Are there too many fraction bits? 911 if (Fraction & ~(A64FracMask << A64FracStart)) 912 return false; 913 914 if (Exponent < -3 || Exponent > 4) 915 return false; 916 917 uint32_t PackedFraction = (Fraction >> A64FracStart) & A64FracMask; 918 uint32_t PackedExp = (Exponent + 7) & 0x7; 919 920 Imm8Bits = (Sign << 7) | (PackedExp << 4) | PackedFraction; 921 return true; 922 } 923 924 // Encoding of the immediate for logical (immediate) instructions: 925 // 926 // | N | imms | immr | size | R | S | 927 // |---+--------+--------+------+--------------+--------------| 928 // | 1 | ssssss | rrrrrr | 64 | UInt(rrrrrr) | UInt(ssssss) | 929 // | 0 | 0sssss | xrrrrr | 32 | UInt(rrrrr) | UInt(sssss) | 930 // | 0 | 10ssss | xxrrrr | 16 | UInt(rrrr) | UInt(ssss) | 931 // | 0 | 110sss | xxxrrr | 8 | UInt(rrr) | UInt(sss) | 932 // | 0 | 1110ss | xxxxrr | 4 | UInt(rr) | UInt(ss) | 933 // | 0 | 11110s | xxxxxr | 2 | UInt(r) | UInt(s) | 934 // | 0 | 11111x | - | | UNALLOCATED | | 935 // 936 // Columns 'R', 'S' and 'size' specify a "bitmask immediate" of size bits in 937 // which the lower S+1 bits are ones and the remaining bits are zero, then 938 // rotated right by R bits, which is then replicated across the datapath. 939 // 940 // + Values of 'N', 'imms' and 'immr' which do not match the above table are 941 // RESERVED. 942 // + If all 's' bits in the imms field are set then the instruction is 943 // RESERVED. 944 // + The 'x' bits in the 'immr' field are IGNORED. 945 946 bool A64Imms::isLogicalImm(unsigned RegWidth, uint64_t Imm, uint32_t &Bits) { 947 int RepeatWidth; 948 int Rotation = 0; 949 int Num1s = 0; 950 951 // Because there are S+1 ones in the replicated mask, an immediate of all 952 // zeros is not allowed. Filtering it here is probably more efficient. 953 if (Imm == 0) return false; 954 955 for (RepeatWidth = RegWidth; RepeatWidth > 1; RepeatWidth /= 2) { 956 uint64_t RepeatMask = RepeatWidth == 64 ? -1 : (1ULL << RepeatWidth) - 1; 957 uint64_t ReplicatedMask = Imm & RepeatMask; 958 959 if (ReplicatedMask == 0) continue; 960 961 // First we have to make sure the mask is actually repeated in each slot for 962 // this width-specifier. 963 bool IsReplicatedMask = true; 964 for (unsigned i = RepeatWidth; i < RegWidth; i += RepeatWidth) { 965 if (((Imm >> i) & RepeatMask) != ReplicatedMask) { 966 IsReplicatedMask = false; 967 break; 968 } 969 } 970 if (!IsReplicatedMask) continue; 971 972 // Now we have to work out the amount of rotation needed. The first part of 973 // this calculation is actually independent of RepeatWidth, but the complex 974 // case will depend on it. 975 Rotation = countTrailingZeros(Imm); 976 if (Rotation == 0) { 977 // There were no leading zeros, which means it's either in place or there 978 // are 1s at each end (e.g. 0x8003 needs rotating). 979 Rotation = RegWidth == 64 ? CountLeadingOnes_64(Imm) 980 : CountLeadingOnes_32(Imm); 981 Rotation = RepeatWidth - Rotation; 982 } 983 984 uint64_t ReplicatedOnes = ReplicatedMask; 985 if (Rotation != 0 && Rotation != 64) 986 ReplicatedOnes = (ReplicatedMask >> Rotation) 987 | ((ReplicatedMask << (RepeatWidth - Rotation)) & RepeatMask); 988 989 // Of course, they may not actually be ones, so we have to check that: 990 if (!isMask_64(ReplicatedOnes)) 991 continue; 992 993 Num1s = CountTrailingOnes_64(ReplicatedOnes); 994 995 // We know we've got an almost valid encoding (certainly, if this is invalid 996 // no other parameters would work). 997 break; 998 } 999 1000 // The encodings which would produce all 1s are RESERVED. 1001 if (RepeatWidth == 1 || Num1s == RepeatWidth) return false; 1002 1003 uint32_t N = RepeatWidth == 64; 1004 uint32_t ImmR = RepeatWidth - Rotation; 1005 uint32_t ImmS = Num1s - 1; 1006 1007 switch (RepeatWidth) { 1008 default: break; // No action required for other valid rotations. 1009 case 16: ImmS |= 0x20; break; // 10ssss 1010 case 8: ImmS |= 0x30; break; // 110sss 1011 case 4: ImmS |= 0x38; break; // 1110ss 1012 case 2: ImmS |= 0x3c; break; // 11110s 1013 } 1014 1015 Bits = ImmS | (ImmR << 6) | (N << 12); 1016 1017 return true; 1018 } 1019 1020 1021 bool A64Imms::isLogicalImmBits(unsigned RegWidth, uint32_t Bits, 1022 uint64_t &Imm) { 1023 uint32_t N = Bits >> 12; 1024 uint32_t ImmR = (Bits >> 6) & 0x3f; 1025 uint32_t ImmS = Bits & 0x3f; 1026 1027 // N=1 encodes a 64-bit replication and is invalid for the 32-bit 1028 // instructions. 1029 if (RegWidth == 32 && N != 0) return false; 1030 1031 int Width = 0; 1032 if (N == 1) 1033 Width = 64; 1034 else if ((ImmS & 0x20) == 0) 1035 Width = 32; 1036 else if ((ImmS & 0x10) == 0) 1037 Width = 16; 1038 else if ((ImmS & 0x08) == 0) 1039 Width = 8; 1040 else if ((ImmS & 0x04) == 0) 1041 Width = 4; 1042 else if ((ImmS & 0x02) == 0) 1043 Width = 2; 1044 else { 1045 // ImmS is 0b11111x: UNALLOCATED 1046 return false; 1047 } 1048 1049 int Num1s = (ImmS & (Width - 1)) + 1; 1050 1051 // All encodings which would map to -1 (signed) are RESERVED. 1052 if (Num1s == Width) return false; 1053 1054 int Rotation = (ImmR & (Width - 1)); 1055 uint64_t Mask = (1ULL << Num1s) - 1; 1056 uint64_t WidthMask = Width == 64 ? -1 : (1ULL << Width) - 1; 1057 if (Rotation != 0 && Rotation != 64) 1058 Mask = (Mask >> Rotation) 1059 | ((Mask << (Width - Rotation)) & WidthMask); 1060 1061 Imm = Mask; 1062 for (unsigned i = 1; i < RegWidth / Width; ++i) { 1063 Mask <<= Width; 1064 Imm |= Mask; 1065 } 1066 1067 return true; 1068 } 1069 1070 bool A64Imms::isMOVZImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) { 1071 // If high bits are set then a 32-bit MOVZ can't possibly work. 1072 if (RegWidth == 32 && (Value & ~0xffffffffULL)) 1073 return false; 1074 1075 for (int i = 0; i < RegWidth; i += 16) { 1076 // If the value is 0 when we mask out all the bits that could be set with 1077 // the current LSL value then it's representable. 1078 if ((Value & ~(0xffffULL << i)) == 0) { 1079 Shift = i / 16; 1080 UImm16 = (Value >> i) & 0xffff; 1081 return true; 1082 } 1083 } 1084 return false; 1085 } 1086 1087 bool A64Imms::isMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) { 1088 // MOVN is defined to set its register to NOT(LSL(imm16, shift)). 1089 1090 // We have to be a little careful about a 32-bit register: 0xffff_1234 *is* 1091 // representable, but ~0xffff_1234 == 0xffff_ffff_0000_edcb which is not 1092 // a valid input for isMOVZImm. 1093 if (RegWidth == 32 && (Value & ~0xffffffffULL)) 1094 return false; 1095 1096 uint64_t MOVZEquivalent = RegWidth == 32 ? ~Value & 0xffffffff : ~Value; 1097 1098 return isMOVZImm(RegWidth, MOVZEquivalent, UImm16, Shift); 1099 } 1100 1101 bool A64Imms::isOnlyMOVNImm(int RegWidth, uint64_t Value, 1102 int &UImm16, int &Shift) { 1103 if (isMOVZImm(RegWidth, Value, UImm16, Shift)) 1104 return false; 1105 1106 return isMOVNImm(RegWidth, Value, UImm16, Shift); 1107 } 1108 1109 // decodeNeonModShiftImm - Decode a Neon OpCmode value into the 1110 // the shift amount and the shift type (shift zeros or ones in) and 1111 // returns whether the OpCmode value implies a shift operation. 1112 bool A64Imms::decodeNeonModShiftImm(unsigned OpCmode, unsigned &ShiftImm, 1113 unsigned &ShiftOnesIn) { 1114 ShiftImm = 0; 1115 ShiftOnesIn = false; 1116 bool HasShift = true; 1117 1118 if (OpCmode == 0xe) { 1119 // movi byte 1120 HasShift = false; 1121 } else if (OpCmode == 0x1e) { 1122 // movi 64-bit bytemask 1123 HasShift = false; 1124 } else if ((OpCmode & 0xc) == 0x8) { 1125 // shift zeros, per halfword 1126 ShiftImm = ((OpCmode & 0x2) >> 1); 1127 } else if ((OpCmode & 0x8) == 0) { 1128 // shift zeros, per word 1129 ShiftImm = ((OpCmode & 0x6) >> 1); 1130 } else if ((OpCmode & 0xe) == 0xc) { 1131 // shift ones, per word 1132 ShiftOnesIn = true; 1133 ShiftImm = (OpCmode & 0x1); 1134 } else { 1135 // per byte, per bytemask 1136 llvm_unreachable("Unsupported Neon modified immediate"); 1137 } 1138 1139 return HasShift; 1140 } 1141 1142 // decodeNeonModImm - Decode a NEON modified immediate and OpCmode values 1143 // into the element value and the element size in bits. 1144 uint64_t A64Imms::decodeNeonModImm(unsigned Val, unsigned OpCmode, 1145 unsigned &EltBits) { 1146 uint64_t DecodedVal = Val; 1147 EltBits = 0; 1148 1149 if (OpCmode == 0xe) { 1150 // movi byte 1151 EltBits = 8; 1152 } else if (OpCmode == 0x1e) { 1153 // movi 64-bit bytemask 1154 DecodedVal = 0; 1155 for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) { 1156 if ((Val >> ByteNum) & 1) 1157 DecodedVal |= (uint64_t)0xff << (8 * ByteNum); 1158 } 1159 EltBits = 64; 1160 } else if ((OpCmode & 0xc) == 0x8) { 1161 // shift zeros, per halfword 1162 EltBits = 16; 1163 } else if ((OpCmode & 0x8) == 0) { 1164 // shift zeros, per word 1165 EltBits = 32; 1166 } else if ((OpCmode & 0xe) == 0xc) { 1167 // shift ones, per word 1168 EltBits = 32; 1169 } else { 1170 llvm_unreachable("Unsupported Neon modified immediate"); 1171 } 1172 return DecodedVal; 1173 } 1174
