1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Interface definition of the TargetLowering class that is common 12 /// to all AMD GPUs. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef AMDGPUISELLOWERING_H 17 #define AMDGPUISELLOWERING_H 18 19 #include "llvm/Target/TargetLowering.h" 20 21 namespace llvm { 22 23 class AMDGPUMachineFunction; 24 class MachineRegisterInfo; 25 26 class AMDGPUTargetLowering : public TargetLowering { 27 private: 28 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 29 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 30 31 protected: 32 33 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's 34 /// MachineFunction. 35 /// 36 /// \returns a RegisterSDNode representing Reg. 37 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, 38 const TargetRegisterClass *RC, 39 unsigned Reg, EVT VT) const; 40 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 41 SelectionDAG &DAG) const; 42 43 bool isHWTrueValue(SDValue Op) const; 44 bool isHWFalseValue(SDValue Op) const; 45 46 void AnalyzeFormalArguments(CCState &State, 47 const SmallVectorImpl<ISD::InputArg> &Ins) const; 48 49 public: 50 AMDGPUTargetLowering(TargetMachine &TM); 51 52 virtual bool isFAbsFree(EVT VT) const; 53 virtual bool isFNegFree(EVT VT) const; 54 virtual MVT getVectorIdxTy() const; 55 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, 56 bool isVarArg, 57 const SmallVectorImpl<ISD::OutputArg> &Outs, 58 const SmallVectorImpl<SDValue> &OutVals, 59 SDLoc DL, SelectionDAG &DAG) const; 60 virtual SDValue LowerCall(CallLoweringInfo &CLI, 61 SmallVectorImpl<SDValue> &InVals) const { 62 CLI.Callee.dump(); 63 llvm_unreachable("Undefined function"); 64 } 65 66 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 67 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; 68 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; 69 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const; 70 virtual const char* getTargetNodeName(unsigned Opcode) const; 71 72 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const { 73 return N; 74 } 75 76 // Functions defined in AMDILISelLowering.cpp 77 public: 78 79 /// \brief Determine which of the bits specified in \p Mask are known to be 80 /// either zero or one and return them in the \p KnownZero and \p KnownOne 81 /// bitsets. 82 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 83 APInt &KnownZero, 84 APInt &KnownOne, 85 const SelectionDAG &DAG, 86 unsigned Depth = 0) const; 87 88 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 89 const CallInst &I, unsigned Intrinsic) const; 90 91 /// We want to mark f32/f64 floating point values as legal. 92 bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 93 94 /// We don't want to shrink f64/f32 constants. 95 bool ShouldShrinkFPConstant(EVT VT) const; 96 97 private: 98 void InitAMDILLowering(); 99 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const; 100 SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const; 101 SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const; 102 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const; 103 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const; 104 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const; 105 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const; 106 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const; 107 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const; 108 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 109 EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const; 110 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 111 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 112 }; 113 114 namespace AMDGPUISD { 115 116 enum { 117 // AMDIL ISD Opcodes 118 FIRST_NUMBER = ISD::BUILTIN_OP_END, 119 CALL, // Function call based on a single integer 120 UMUL, // 32bit unsigned multiplication 121 DIV_INF, // Divide with infinity returned on zero divisor 122 RET_FLAG, 123 BRANCH_COND, 124 // End AMDIL ISD Opcodes 125 DWORDADDR, 126 FRACT, 127 COS_HW, 128 SIN_HW, 129 FMAX, 130 SMAX, 131 UMAX, 132 FMIN, 133 SMIN, 134 UMIN, 135 URECIP, 136 DOT4, 137 TEXTURE_FETCH, 138 EXPORT, 139 CONST_ADDRESS, 140 REGISTER_LOAD, 141 REGISTER_STORE, 142 LAST_AMDGPU_ISD_NUMBER 143 }; 144 145 146 } // End namespace AMDGPUISD 147 148 } // End namespace llvm 149 150 #endif // AMDGPUISELLOWERING_H 151
