1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Interface definition for R600InstrInfo 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef R600INSTRUCTIONINFO_H_ 16 #define R600INSTRUCTIONINFO_H_ 17 18 #include "AMDGPUInstrInfo.h" 19 #include "R600Defines.h" 20 #include "R600RegisterInfo.h" 21 #include <map> 22 23 namespace llvm { 24 25 class AMDGPUTargetMachine; 26 class DFAPacketizer; 27 class ScheduleDAG; 28 class MachineFunction; 29 class MachineInstr; 30 class MachineInstrBuilder; 31 32 class R600InstrInfo : public AMDGPUInstrInfo { 33 private: 34 const R600RegisterInfo RI; 35 36 std::vector<std::pair<int, unsigned> > 37 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const; 38 39 40 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 41 MachineBasicBlock::iterator I, 42 unsigned ValueReg, unsigned Address, 43 unsigned OffsetReg, 44 unsigned AddrChan) const; 45 46 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 47 MachineBasicBlock::iterator I, 48 unsigned ValueReg, unsigned Address, 49 unsigned OffsetReg, 50 unsigned AddrChan) const; 51 public: 52 enum BankSwizzle { 53 ALU_VEC_012_SCL_210 = 0, 54 ALU_VEC_021_SCL_122, 55 ALU_VEC_120_SCL_212, 56 ALU_VEC_102_SCL_221, 57 ALU_VEC_201, 58 ALU_VEC_210 59 }; 60 61 explicit R600InstrInfo(const AMDGPUSubtarget &st); 62 63 const R600RegisterInfo &getRegisterInfo() const override; 64 void copyPhysReg(MachineBasicBlock &MBB, 65 MachineBasicBlock::iterator MI, DebugLoc DL, 66 unsigned DestReg, unsigned SrcReg, 67 bool KillSrc) const override; 68 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 69 MachineBasicBlock::iterator MBBI) const override; 70 71 bool isTrig(const MachineInstr &MI) const; 72 bool isPlaceHolderOpcode(unsigned opcode) const; 73 bool isReductionOp(unsigned opcode) const; 74 bool isCubeOp(unsigned opcode) const; 75 76 /// \returns true if this \p Opcode represents an ALU instruction. 77 bool isALUInstr(unsigned Opcode) const; 78 bool hasInstrModifiers(unsigned Opcode) const; 79 bool isLDSInstr(unsigned Opcode) const; 80 bool isLDSNoRetInstr(unsigned Opcode) const; 81 bool isLDSRetInstr(unsigned Opcode) const; 82 83 /// \returns true if this \p Opcode represents an ALU instruction or an 84 /// instruction that will be lowered in ExpandSpecialInstrs Pass. 85 bool canBeConsideredALU(const MachineInstr *MI) const; 86 87 bool isTransOnly(unsigned Opcode) const; 88 bool isTransOnly(const MachineInstr *MI) const; 89 bool isVectorOnly(unsigned Opcode) const; 90 bool isVectorOnly(const MachineInstr *MI) const; 91 bool isExport(unsigned Opcode) const; 92 93 bool usesVertexCache(unsigned Opcode) const; 94 bool usesVertexCache(const MachineInstr *MI) const; 95 bool usesTextureCache(unsigned Opcode) const; 96 bool usesTextureCache(const MachineInstr *MI) const; 97 98 bool mustBeLastInClause(unsigned Opcode) const; 99 bool usesAddressRegister(MachineInstr *MI) const; 100 bool definesAddressRegister(MachineInstr *MI) const; 101 bool readsLDSSrcReg(const MachineInstr *MI) const; 102 103 /// \returns The operand index for the given source number. Legal values 104 /// for SrcNum are 0, 1, and 2. 105 int getSrcIdx(unsigned Opcode, unsigned SrcNum) const; 106 /// \returns The operand Index for the Sel operand given an index to one 107 /// of the instruction's src operands. 108 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const; 109 110 /// \returns a pair for each src of an ALU instructions. 111 /// The first member of a pair is the register id. 112 /// If register is ALU_CONST, second member is SEL. 113 /// If register is ALU_LITERAL, second member is IMM. 114 /// Otherwise, second member value is undefined. 115 SmallVector<std::pair<MachineOperand *, int64_t>, 3> 116 getSrcs(MachineInstr *MI) const; 117 118 unsigned isLegalUpTo( 119 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, 120 const std::vector<R600InstrInfo::BankSwizzle> &Swz, 121 const std::vector<std::pair<int, unsigned> > &TransSrcs, 122 R600InstrInfo::BankSwizzle TransSwz) const; 123 124 bool FindSwizzleForVectorSlot( 125 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, 126 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, 127 const std::vector<std::pair<int, unsigned> > &TransSrcs, 128 R600InstrInfo::BankSwizzle TransSwz) const; 129 130 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 131 /// returns true and the first (in lexical order) BankSwizzle affectation 132 /// starting from the one already provided in the Instruction Group MIs that 133 /// fits Read Port limitations in BS if available. Otherwise returns false 134 /// and undefined content in BS. 135 /// isLastAluTrans should be set if the last Alu of MIs will be executed on 136 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to 137 /// apply to the last instruction. 138 /// PV holds GPR to PV registers in the Instruction Group MIs. 139 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs, 140 const DenseMap<unsigned, unsigned> &PV, 141 std::vector<BankSwizzle> &BS, 142 bool isLastAluTrans) const; 143 144 /// An instruction group can only access 2 channel pair (either [XY] or [ZW]) 145 /// from KCache bank on R700+. This function check if MI set in input meet 146 /// this limitations 147 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const; 148 /// Same but using const index set instead of MI set. 149 bool fitsConstReadLimitations(const std::vector<unsigned>&) const; 150 151 /// \brief Vector instructions are instructions that must fill all 152 /// instruction slots within an instruction group. 153 bool isVector(const MachineInstr &MI) const; 154 155 unsigned getIEQOpcode() const override; 156 bool isMov(unsigned Opcode) const override; 157 158 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM, 159 const ScheduleDAG *DAG) const override; 160 161 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 162 163 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 164 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; 165 166 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override; 167 168 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 169 170 bool isPredicated(const MachineInstr *MI) const override; 171 172 bool isPredicable(MachineInstr *MI) const override; 173 174 bool 175 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 176 const BranchProbability &Probability) const override; 177 178 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 179 unsigned ExtraPredCycles, 180 const BranchProbability &Probability) const override ; 181 182 bool 183 isProfitableToIfCvt(MachineBasicBlock &TMBB, 184 unsigned NumTCycles, unsigned ExtraTCycles, 185 MachineBasicBlock &FMBB, 186 unsigned NumFCycles, unsigned ExtraFCycles, 187 const BranchProbability &Probability) const override; 188 189 bool DefinesPredicate(MachineInstr *MI, 190 std::vector<MachineOperand> &Pred) const override; 191 192 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 193 const SmallVectorImpl<MachineOperand> &Pred2) const override; 194 195 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 196 MachineBasicBlock &FMBB) const override; 197 198 bool PredicateInstruction(MachineInstr *MI, 199 const SmallVectorImpl<MachineOperand> &Pred) const override; 200 201 unsigned int getPredicationCost(const MachineInstr *) const override; 202 203 unsigned int getInstrLatency(const InstrItineraryData *ItinData, 204 const MachineInstr *MI, 205 unsigned *PredCost = nullptr) const override; 206 207 int getInstrLatency(const InstrItineraryData *ItinData, 208 SDNode *Node) const override { return 1;} 209 210 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 211 212 /// \brief Reserve the registers that may be accesed using indirect addressing. 213 void reserveIndirectRegisters(BitVector &Reserved, 214 const MachineFunction &MF) const; 215 216 unsigned calculateIndirectAddress(unsigned RegIndex, 217 unsigned Channel) const override; 218 219 const TargetRegisterClass *getIndirectAddrRegClass() const override; 220 221 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 222 MachineBasicBlock::iterator I, 223 unsigned ValueReg, unsigned Address, 224 unsigned OffsetReg) const override; 225 226 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 227 MachineBasicBlock::iterator I, 228 unsigned ValueReg, unsigned Address, 229 unsigned OffsetReg) const override; 230 231 unsigned getMaxAlusPerClause() const; 232 233 ///buildDefaultInstruction - This function returns a MachineInstr with 234 /// all the instruction modifiers initialized to their default values. 235 /// You can use this function to avoid manually specifying each instruction 236 /// modifier operand when building a new instruction. 237 /// 238 /// \returns a MachineInstr with all the instruction modifiers initialized 239 /// to their default values. 240 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, 241 MachineBasicBlock::iterator I, 242 unsigned Opcode, 243 unsigned DstReg, 244 unsigned Src0Reg, 245 unsigned Src1Reg = 0) const; 246 247 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB, 248 MachineInstr *MI, 249 unsigned Slot, 250 unsigned DstReg) const; 251 252 MachineInstr *buildMovImm(MachineBasicBlock &BB, 253 MachineBasicBlock::iterator I, 254 unsigned DstReg, 255 uint64_t Imm) const; 256 257 MachineInstr *buildMovInstr(MachineBasicBlock *MBB, 258 MachineBasicBlock::iterator I, 259 unsigned DstReg, unsigned SrcReg) const override; 260 261 /// \brief Get the index of Op in the MachineInstr. 262 /// 263 /// \returns -1 if the Instruction does not contain the specified \p Op. 264 int getOperandIdx(const MachineInstr &MI, unsigned Op) const; 265 266 /// \brief Get the index of \p Op for the given Opcode. 267 /// 268 /// \returns -1 if the Instruction does not contain the specified \p Op. 269 int getOperandIdx(unsigned Opcode, unsigned Op) const; 270 271 /// \brief Helper function for setting instruction flag values. 272 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const; 273 274 /// \returns true if this instruction has an operand for storing target flags. 275 bool hasFlagOperand(const MachineInstr &MI) const; 276 277 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand. 278 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 279 280 ///\brief Determine if the specified \p Flag is set on this \p Operand. 281 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const; 282 283 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2) 284 /// \param Flag The flag being set. 285 /// 286 /// \returns the operand containing the flags for this instruction. 287 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0, 288 unsigned Flag = 0) const; 289 290 /// \brief Clear the specified flag on the instruction. 291 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 292 }; 293 294 namespace AMDGPU { 295 296 int getLDSNoRetOp(uint16_t Opcode); 297 298 } //End namespace AMDGPU 299 300 } // End llvm namespace 301 302 #endif // R600INSTRINFO_H_ 303
