| /external/llvm/lib/Target/NVPTX/ |
| NVPTXImageOptimizer.cpp | 61 Instruction &Instr = *I;
69 Changed |= replaceIsTypePSampler(Instr);
72 Changed |= replaceIsTypePSurface(Instr);
75 Changed |= replaceIsTypePTexture(Instr);
|
| /art/compiler/utils/mips/ |
| constants_mips.h | 89 class Instr {
99 // to allocate or create instances of class Instr.
100 // Use the At(pc) function to create references to Instr.
101 static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); }
104 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
|
| /art/compiler/utils/x86_64/ |
| constants_x86_64.h | 111 class Instr {
123 // to allocate or create instances of class Instr.
124 // Use the At(pc) function to create references to Instr.
125 static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); }
128 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
|
| /external/chromium_org/v8/src/mips/ |
| constants-mips.h | 181 typedef int32_t Instr;
592 extern const Instr kPopInstruction;
594 extern const Instr kPushInstruction;
596 extern const Instr kPushRegPattern;
598 extern const Instr kPopRegPattern;
599 extern const Instr kLwRegFpOffsetPattern;
600 extern const Instr kSwRegFpOffsetPattern;
601 extern const Instr kLwRegFpNegOffsetPattern;
602 extern const Instr kSwRegFpNegOffsetPattern;
604 extern const Instr kRtMask
[all...] |
| /external/llvm/include/llvm/IR/ |
| DiagnosticInfo.h | 106 const Instruction *Instr;
115 Instr(nullptr) {}
124 MsgStr(MsgStr), Instr(nullptr) {}
126 /// \p Instr gives the original instruction that triggered the diagnostic.
136 const Instruction *getInstruction() const { return Instr; }
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| WinCodeViewLineTables.cpp | 176 MCSymbol *Instr = FI.Instrs[J];
177 assert(InstrInfo.count(Instr));
206 EmitLabelDiff(Asm->OutStreamer, Fn, Instr);
207 Asm->EmitInt32(InstrInfo[Instr].LineNumber);
|
| /external/llvm/lib/Target/R600/ |
| R600OptimizeVectorRegisters.cpp | 63 MachineInstr *Instr;
66 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
68 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
69 MachineOperand &MO = Instr->getOperand(i);
70 unsigned Chan = Instr->getOperand(i + 1).getImm();
80 return RSI.Instr == Instr;
180 unsigned Reg = RSI->Instr->getOperand(0).getReg();
181 MachineBasicBlock::iterator Pos = RSI->Instr;
185 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg()
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| BypassSlowDivision.cpp | 85 Instruction *Instr = J;
86 Value *Dividend = Instr->getOperand(0);
87 Value *Divisor = Instr->getOperand(1);
142 PHINode *QuoPhi = SuccessorBuilder.CreatePHI(Instr->getType(), 2);
145 PHINode *RemPhi = SuccessorBuilder.CreatePHI(Instr->getType(), 2);
149 // Replace Instr with appropriate phi node
151 Instr->replaceAllUsesWith(QuoPhi);
153 Instr->replaceAllUsesWith(RemPhi);
154 Instr->eraseFromParent();
193 Instruction *Instr = J
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 307 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
308 assert(Instr && "Missing target independent instruction");
309 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
310 InstrsByEnum.push_back(Instr);
321 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
|
| CodeGenDAGPatterns.cpp | [all...] |
| /art/compiler/utils/x86/ |
| constants_x86.h | 103 class Instr {
115 // to allocate or create instances of class Instr.
116 // Use the At(pc) function to create references to Instr.
117 static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); }
120 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 616 static bool UpdateOperandRegClass(MachineInstr *Instr) {
617 MachineBasicBlock *MBB = Instr->getParent();
626 for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx;
628 MachineOperand &MO = Instr->getOperand(OpIdx);
630 Instr->getRegClassConstraint(OpIdx, TII, TRI);
727 const MachineInstr &Instr = *I;
729 if (Instr.modifiesRegister(AArch64::NZCV, TRI) ||
730 Instr.readsRegister(AArch64::NZCV, TRI))
778 const MachineInstr &Instr = *I;
779 for (unsigned IO = 0, EO = Instr.getNumOperands(); !IsSafe && IO != EO
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| instructions-arm64.h | 19 typedef uint32_t Instr;
99 V8_INLINE Instr InstructionBits() const {
100 return *reinterpret_cast<const Instr*>(this);
103 V8_INLINE void SetInstructionBits(Instr new_instr) {
104 *reinterpret_cast<Instr*>(this) = new_instr;
120 Instr Mask(uint32_t mask) const {
291 // The range of the branch instruction, expressed as 'instr +- range'.
410 const Instr kImmExceptionIsRedirectedCall = 0xca11;
414 const Instr kImmExceptionIsUnreachable = 0xdebf;
418 const Instr kImmExceptionIsPrintf = 0xdeb1
[all...] |
| /external/llvm/tools/llvm-stress/ |
| llvm-stress.cpp | 673 Instruction *Instr = *it;
674 BasicBlock *Curr = Instr->getParent();
675 BasicBlock::iterator Loc= Instr;
677 Instr->moveBefore(Curr->getTerminator());
679 BranchInst::Create(Curr, Next, Instr, Curr->getTerminator());
|
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAG.h | 260 MachineInstr *Instr; // Alternatively, a MachineInstr.
320 : Node(node), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr),
335 SUnit(MachineInstr *instr, unsigned nodenum)
336 : Node(nullptr), Instr(instr), OrigNode(nullptr), SchedClass(nullptr),
351 : Node(nullptr), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr),
376 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
383 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
389 bool isInstr() const { return Instr; }
395 Instr = MI
[all...] |
| /external/llvm/lib/Analysis/IPA/ |
| InlineCost.cpp | [all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | [all...] |
| /external/vixl/src/a64/ |
| instructions-a64.h | 37 typedef uint32_t Instr;
156 inline Instr InstructionBits() const {
157 return *(reinterpret_cast<const Instr*>(this));
160 inline void SetInstructionBits(Instr new_instr) {
161 *(reinterpret_cast<Instr*>(this)) = new_instr;
177 inline Instr Mask(uint32_t mask) const {
|
| /art/compiler/utils/arm/ |
| constants_arm.h | 39 // General constants are in an anonymous enum in class Instr.
220 // The class Instr enables access to individual fields defined in the ARM
227 // Instr* instr = Instr::At(ptr);
228 // int type = instr->TypeField();
229 // return ((type == 0) || (type == 1)) && instr->HasS();
232 class Instr {
436 // to allocate or create instances of class Instr.
437 // Use the At(pc) function to create references to Instr
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 41 #define DEBUG_TYPE "ppc-instr-info"
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 159 FAddCombine(InstCombiner::BuilderTy *B) : Builder(B), Instr(nullptr) {}
183 Instruction *Instr;
461 // Input Instr I Factor AddSub0 AddSub1
528 Instr = I;
689 Result = ConstantFP::get(Instr->getType(), 0.0);
794 NewInstr->setDebugLoc(Instr->getDebugLoc());
801 NewInstr->setFastMathFlags(Instr->getFastMathFlags());
849 return Coeff.getValue(Instr->getType());
865 return createFMul(OpndVal, Coeff.getValue(Instr->getType()));
[all...] |
| /external/chromium_org/v8/src/arm/ |
| constants-arm.h | 25 inline int DecodeConstantPoolLength(int instr) {
26 ASSERT((instr & kConstantPoolMarkerMask) == kConstantPoolMarker);
27 return ((instr >> 4) & 0xfff0) | (instr & 0xf);
55 // General constants are in an anonymous enum in class Instr.
120 // Instr is merely used by the Assembler to distinguish 32bit integers
124 typedef int32_t Instr;
415 extern const Instr kPopInstruction;
419 extern const Instr kPushRegPattern;
423 extern const Instr kPopRegPattern
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 579 // If this machine instr is an inline asm, measure it.
598 // If this machine instr is a constant pool entry, its size is recorded as
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | 42 #define DEBUG_TYPE "x86-instr-info"
[all...] |
| /external/llvm/bindings/ocaml/llvm/ |
| llvm_ocaml.c | [all...] |
