| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 97 unsigned NewReg;
103 NewReg = AArch64::WZR;
106 NewReg = AArch64::XZR;
110 MO.setReg(NewReg);
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 278 MCOperand NewReg;
283 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
285 NewMI.addOperand(NewReg);
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| ExprEngineCXX.cpp | 435 const MemRegion *NewReg = symVal.castAs<loc::MemRegionVal>().getRegion();
438 getStoreManager().GetElementZeroRegion(NewReg, ObjTy);
|
| /external/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.cpp | 343 // be replaced by NewReg. Return true if any of their parent instructions may
348 // the two-address instruction also defines NewReg, as may happen with
352 // both NewReg and AntiDepReg covers it.
356 unsigned NewReg)
362 // operands, in case they may be assigned to NewReg. In this case antidep
367 // Handle cases in which this instruction defines NewReg.
372 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
376 CheckOper.getReg() != NewReg)
379 // Don't allow the instruction to define NewReg and AntiDepReg.
385 // NewReg
[all...] |
| MachineCSE.cpp | 530 unsigned NewReg = CSMI->getOperand(i).getReg();
536 if (OldReg == NewReg) {
542 TargetRegisterInfo::isVirtualRegister(NewReg) &&
545 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
554 if (!MRI->constrainRegClass(NewReg, OldRC)) {
560 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
|
| TailDuplication.cpp | 88 void AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
379 void TailDuplicatePass::AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
383 LI->second.push_back(std::make_pair(BB, NewReg));
386 Vals.push_back(std::make_pair(BB, NewReg));
442 unsigned NewReg = MRI->createVirtualRegister(RC);
443 MO.setReg(NewReg);
444 LocalVRMap.insert(std::make_pair(Reg, NewReg));
446 AddSSAUpdateEntry(Reg, NewReg, PredBB);
[all...] |
| TwoAddressInstructionPass.cpp | 665 unsigned NewReg = 0;
668 NewReg, IsDstPhys)) {
678 VirtRegPairs.push_back(NewReg);
681 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
683 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
684 VirtRegPairs.push_back(NewReg);
685 Reg = NewReg;
[all...] |
| RegisterCoalescer.cpp | 613 unsigned NewReg = NewDstMO.getReg();
614 if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill())
676 UseMO.setReg(NewReg);
685 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
686 UseMO.substPhysReg(NewReg, *TRI);
688 UseMO.setReg(NewReg);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 653 unsigned NewReg = optimizeSDPattern(MI);
655 if (NewReg != 0) {
661 // reference into a plain DPR, and that will end poorly. NewReg is
664 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
668 << PrintReg(NewReg) << "\n");
669 (*I)->substVirtReg(NewReg, 0, *TRI);
672 Replacements[MI] = NewReg;
|
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 580 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
581 return NewReg;
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 597 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
598 Elts.insert(NewReg);
604 NewReg->addSuperClass(Supers[i], Ranges[i]);
611 if (NewReg->getValue(RV.getNameInit()))
635 NewReg->addValue(*Def->getValue(Field));
644 NewReg->addValue(*DefRV);
649 NewReg->addValue(RV);
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
