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      1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef X86SUBTARGET_H
     15 #define X86SUBTARGET_H
     16 
     17 #include "X86FrameLowering.h"
     18 #include "X86ISelLowering.h"
     19 #include "X86InstrInfo.h"
     20 #include "X86JITInfo.h"
     21 #include "X86SelectionDAGInfo.h"
     22 #include "llvm/ADT/Triple.h"
     23 #include "llvm/IR/CallingConv.h"
     24 #include "llvm/Target/TargetSubtargetInfo.h"
     25 #include <string>
     26 
     27 #define GET_SUBTARGETINFO_HEADER
     28 #include "X86GenSubtargetInfo.inc"
     29 
     30 namespace llvm {
     31 class GlobalValue;
     32 class StringRef;
     33 class TargetMachine;
     34 
     35 /// PICStyles - The X86 backend supports a number of different styles of PIC.
     36 ///
     37 namespace PICStyles {
     38 enum Style {
     39   StubPIC,          // Used on i386-darwin in -fPIC mode.
     40   StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
     41   GOT,              // Used on many 32-bit unices in -fPIC mode.
     42   RIPRel,           // Used on X86-64 when not in -static mode.
     43   None              // Set when in -static mode (not PIC or DynamicNoPIC mode).
     44 };
     45 }
     46 
     47 class X86Subtarget final : public X86GenSubtargetInfo {
     48 
     49 protected:
     50   enum X86SSEEnum {
     51     NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
     52   };
     53 
     54   enum X863DNowEnum {
     55     NoThreeDNow, ThreeDNow, ThreeDNowA
     56   };
     57 
     58   enum X86ProcFamilyEnum {
     59     Others, IntelAtom, IntelSLM
     60   };
     61 
     62   /// X86ProcFamily - X86 processor family: Intel Atom, and others
     63   X86ProcFamilyEnum X86ProcFamily;
     64 
     65   /// PICStyle - Which PIC style to use
     66   ///
     67   PICStyles::Style PICStyle;
     68 
     69   /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
     70   /// none supported.
     71   X86SSEEnum X86SSELevel;
     72 
     73   /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
     74   ///
     75   X863DNowEnum X863DNowLevel;
     76 
     77   /// HasCMov - True if this processor has conditional move instructions
     78   /// (generally pentium pro+).
     79   bool HasCMov;
     80 
     81   /// HasX86_64 - True if the processor supports X86-64 instructions.
     82   ///
     83   bool HasX86_64;
     84 
     85   /// HasPOPCNT - True if the processor supports POPCNT.
     86   bool HasPOPCNT;
     87 
     88   /// HasSSE4A - True if the processor supports SSE4A instructions.
     89   bool HasSSE4A;
     90 
     91   /// HasAES - Target has AES instructions
     92   bool HasAES;
     93 
     94   /// HasPCLMUL - Target has carry-less multiplication
     95   bool HasPCLMUL;
     96 
     97   /// HasFMA - Target has 3-operand fused multiply-add
     98   bool HasFMA;
     99 
    100   /// HasFMA4 - Target has 4-operand fused multiply-add
    101   bool HasFMA4;
    102 
    103   /// HasXOP - Target has XOP instructions
    104   bool HasXOP;
    105 
    106   /// HasTBM - Target has TBM instructions.
    107   bool HasTBM;
    108 
    109   /// HasMOVBE - True if the processor has the MOVBE instruction.
    110   bool HasMOVBE;
    111 
    112   /// HasRDRAND - True if the processor has the RDRAND instruction.
    113   bool HasRDRAND;
    114 
    115   /// HasF16C - Processor has 16-bit floating point conversion instructions.
    116   bool HasF16C;
    117 
    118   /// HasFSGSBase - Processor has FS/GS base insturctions.
    119   bool HasFSGSBase;
    120 
    121   /// HasLZCNT - Processor has LZCNT instruction.
    122   bool HasLZCNT;
    123 
    124   /// HasBMI - Processor has BMI1 instructions.
    125   bool HasBMI;
    126 
    127   /// HasBMI2 - Processor has BMI2 instructions.
    128   bool HasBMI2;
    129 
    130   /// HasRTM - Processor has RTM instructions.
    131   bool HasRTM;
    132 
    133   /// HasHLE - Processor has HLE.
    134   bool HasHLE;
    135 
    136   /// HasADX - Processor has ADX instructions.
    137   bool HasADX;
    138 
    139   /// HasSHA - Processor has SHA instructions.
    140   bool HasSHA;
    141 
    142   /// HasPRFCHW - Processor has PRFCHW instructions.
    143   bool HasPRFCHW;
    144 
    145   /// HasRDSEED - Processor has RDSEED instructions.
    146   bool HasRDSEED;
    147 
    148   /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
    149   bool IsBTMemSlow;
    150 
    151   /// IsSHLDSlow - True if SHLD instructions are slow.
    152   bool IsSHLDSlow;
    153 
    154   /// IsUAMemFast - True if unaligned memory access is fast.
    155   bool IsUAMemFast;
    156 
    157   /// HasVectorUAMem - True if SIMD operations can have unaligned memory
    158   /// operands. This may require setting a feature bit in the processor.
    159   bool HasVectorUAMem;
    160 
    161   /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
    162   /// this is true for most x86-64 chips, but not the first AMD chips.
    163   bool HasCmpxchg16b;
    164 
    165   /// UseLeaForSP - True if the LEA instruction should be used for adjusting
    166   /// the stack pointer. This is an optimization for Intel Atom processors.
    167   bool UseLeaForSP;
    168 
    169   /// HasSlowDivide - True if smaller divides are significantly faster than
    170   /// full divides and should be used when possible.
    171   bool HasSlowDivide;
    172 
    173   /// PostRAScheduler - True if using post-register-allocation scheduler.
    174   bool PostRAScheduler;
    175 
    176   /// PadShortFunctions - True if the short functions should be padded to prevent
    177   /// a stall when returning too early.
    178   bool PadShortFunctions;
    179 
    180   /// CallRegIndirect - True if the Calls with memory reference should be converted
    181   /// to a register-based indirect call.
    182   bool CallRegIndirect;
    183   /// LEAUsesAG - True if the LEA instruction inputs have to be ready at
    184   ///             address generation (AG) time.
    185   bool LEAUsesAG;
    186 
    187   /// SlowLEA - True if the LEA instruction with certain arguments is slow
    188   bool SlowLEA;
    189 
    190   /// SlowIncDec - True if INC and DEC instructions are slow when writing to flags
    191   bool SlowIncDec;
    192 
    193   /// Processor has AVX-512 PreFetch Instructions
    194   bool HasPFI;
    195 
    196   /// Processor has AVX-512 Exponential and Reciprocal Instructions
    197   bool HasERI;
    198 
    199   /// Processor has AVX-512 Conflict Detection Instructions
    200   bool HasCDI;
    201 
    202   /// stackAlignment - The minimum alignment known to hold of the stack frame on
    203   /// entry to the function and which must be maintained by every function.
    204   unsigned stackAlignment;
    205 
    206   /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
    207   ///
    208   unsigned MaxInlineSizeThreshold;
    209 
    210   /// TargetTriple - What processor and OS we're targeting.
    211   Triple TargetTriple;
    212 
    213   /// Instruction itineraries for scheduling
    214   InstrItineraryData InstrItins;
    215 
    216 private:
    217   /// StackAlignOverride - Override the stack alignment.
    218   unsigned StackAlignOverride;
    219 
    220   /// In64BitMode - True if compiling for 64-bit, false for 16-bit or 32-bit.
    221   bool In64BitMode;
    222 
    223   /// In32BitMode - True if compiling for 32-bit, false for 16-bit or 64-bit.
    224   bool In32BitMode;
    225 
    226   /// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit.
    227   bool In16BitMode;
    228 
    229   // Calculates type size & alignment
    230   const DataLayout DL;
    231   X86SelectionDAGInfo TSInfo;
    232   // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
    233   // X86TargetLowering needs.
    234   X86InstrInfo InstrInfo;
    235   X86TargetLowering TLInfo;
    236   X86FrameLowering FrameLowering;
    237   X86JITInfo JITInfo;
    238 
    239 public:
    240   /// This constructor initializes the data members to match that
    241   /// of the specified triple.
    242   ///
    243   X86Subtarget(const std::string &TT, const std::string &CPU,
    244                const std::string &FS, X86TargetMachine &TM,
    245                unsigned StackAlignOverride);
    246 
    247   const X86TargetLowering *getTargetLowering() const { return &TLInfo; }
    248   const X86InstrInfo *getInstrInfo() const { return &InstrInfo; }
    249   const DataLayout *getDataLayout() const { return &DL; }
    250   const X86FrameLowering *getFrameLowering() const { return &FrameLowering; }
    251   const X86SelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
    252   X86JITInfo *getJITInfo() { return &JITInfo; }
    253 
    254   /// getStackAlignment - Returns the minimum alignment known to hold of the
    255   /// stack frame on entry to the function and which must be maintained by every
    256   /// function for this subtarget.
    257   unsigned getStackAlignment() const { return stackAlignment; }
    258 
    259   /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
    260   /// that still makes it profitable to inline the call.
    261   unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
    262 
    263   /// ParseSubtargetFeatures - Parses features string setting specified
    264   /// subtarget options.  Definition of function is auto generated by tblgen.
    265   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
    266 
    267   /// \brief Reset the features for the X86 target.
    268   void resetSubtargetFeatures(const MachineFunction *MF) override;
    269 private:
    270   /// \brief Initialize the full set of dependencies so we can use an initializer
    271   /// list for X86Subtarget.
    272   X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
    273   void initializeEnvironment();
    274   void resetSubtargetFeatures(StringRef CPU, StringRef FS);
    275 public:
    276   /// Is this x86_64? (disregarding specific ABI / programming model)
    277   bool is64Bit() const {
    278     return In64BitMode;
    279   }
    280 
    281   bool is32Bit() const {
    282     return In32BitMode;
    283   }
    284 
    285   bool is16Bit() const {
    286     return In16BitMode;
    287   }
    288 
    289   /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
    290   bool isTarget64BitILP32() const {
    291     return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
    292                            TargetTriple.getOS() == Triple::NaCl);
    293   }
    294 
    295   /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
    296   bool isTarget64BitLP64() const {
    297     return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32);
    298   }
    299 
    300   PICStyles::Style getPICStyle() const { return PICStyle; }
    301   void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
    302 
    303   bool hasCMov() const { return HasCMov; }
    304   bool hasMMX() const { return X86SSELevel >= MMX; }
    305   bool hasSSE1() const { return X86SSELevel >= SSE1; }
    306   bool hasSSE2() const { return X86SSELevel >= SSE2; }
    307   bool hasSSE3() const { return X86SSELevel >= SSE3; }
    308   bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
    309   bool hasSSE41() const { return X86SSELevel >= SSE41; }
    310   bool hasSSE42() const { return X86SSELevel >= SSE42; }
    311   bool hasAVX() const { return X86SSELevel >= AVX; }
    312   bool hasAVX2() const { return X86SSELevel >= AVX2; }
    313   bool hasAVX512() const { return X86SSELevel >= AVX512F; }
    314   bool hasFp256() const { return hasAVX(); }
    315   bool hasInt256() const { return hasAVX2(); }
    316   bool hasSSE4A() const { return HasSSE4A; }
    317   bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
    318   bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
    319   bool hasPOPCNT() const { return HasPOPCNT; }
    320   bool hasAES() const { return HasAES; }
    321   bool hasPCLMUL() const { return HasPCLMUL; }
    322   bool hasFMA() const { return HasFMA; }
    323   // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
    324   bool hasFMA4() const { return HasFMA4 && !HasFMA; }
    325   bool hasXOP() const { return HasXOP; }
    326   bool hasTBM() const { return HasTBM; }
    327   bool hasMOVBE() const { return HasMOVBE; }
    328   bool hasRDRAND() const { return HasRDRAND; }
    329   bool hasF16C() const { return HasF16C; }
    330   bool hasFSGSBase() const { return HasFSGSBase; }
    331   bool hasLZCNT() const { return HasLZCNT; }
    332   bool hasBMI() const { return HasBMI; }
    333   bool hasBMI2() const { return HasBMI2; }
    334   bool hasRTM() const { return HasRTM; }
    335   bool hasHLE() const { return HasHLE; }
    336   bool hasADX() const { return HasADX; }
    337   bool hasSHA() const { return HasSHA; }
    338   bool hasPRFCHW() const { return HasPRFCHW; }
    339   bool hasRDSEED() const { return HasRDSEED; }
    340   bool isBTMemSlow() const { return IsBTMemSlow; }
    341   bool isSHLDSlow() const { return IsSHLDSlow; }
    342   bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
    343   bool hasVectorUAMem() const { return HasVectorUAMem; }
    344   bool hasCmpxchg16b() const { return HasCmpxchg16b; }
    345   bool useLeaForSP() const { return UseLeaForSP; }
    346   bool hasSlowDivide() const { return HasSlowDivide; }
    347   bool padShortFunctions() const { return PadShortFunctions; }
    348   bool callRegIndirect() const { return CallRegIndirect; }
    349   bool LEAusesAG() const { return LEAUsesAG; }
    350   bool slowLEA() const { return SlowLEA; }
    351   bool slowIncDec() const { return SlowIncDec; }
    352   bool hasCDI() const { return HasCDI; }
    353   bool hasPFI() const { return HasPFI; }
    354   bool hasERI() const { return HasERI; }
    355 
    356   bool isAtom() const { return X86ProcFamily == IntelAtom; }
    357   bool isSLM() const { return X86ProcFamily == IntelSLM; }
    358 
    359   const Triple &getTargetTriple() const { return TargetTriple; }
    360 
    361   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
    362   bool isTargetFreeBSD() const {
    363     return TargetTriple.getOS() == Triple::FreeBSD;
    364   }
    365   bool isTargetSolaris() const {
    366     return TargetTriple.getOS() == Triple::Solaris;
    367   }
    368 
    369   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
    370   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
    371   bool isTargetMacho() const { return TargetTriple.isOSBinFormatMachO(); }
    372 
    373   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
    374   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
    375   bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
    376   bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
    377 
    378   bool isTargetWindowsMSVC() const {
    379     return TargetTriple.isWindowsMSVCEnvironment();
    380   }
    381 
    382   bool isTargetKnownWindowsMSVC() const {
    383     return TargetTriple.isKnownWindowsMSVCEnvironment();
    384   }
    385 
    386   bool isTargetWindowsCygwin() const {
    387     return TargetTriple.isWindowsCygwinEnvironment();
    388   }
    389 
    390   bool isTargetWindowsGNU() const {
    391     return TargetTriple.isWindowsGNUEnvironment();
    392   }
    393 
    394   bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
    395 
    396   bool isOSWindows() const { return TargetTriple.isOSWindows(); }
    397 
    398   bool isTargetWin64() const {
    399     return In64BitMode && TargetTriple.isOSWindows();
    400   }
    401 
    402   bool isTargetWin32() const {
    403     return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
    404   }
    405 
    406   bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
    407   bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
    408   bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
    409 
    410   bool isPICStyleStubPIC() const {
    411     return PICStyle == PICStyles::StubPIC;
    412   }
    413 
    414   bool isPICStyleStubNoDynamic() const {
    415     return PICStyle == PICStyles::StubDynamicNoPIC;
    416   }
    417   bool isPICStyleStubAny() const {
    418     return PICStyle == PICStyles::StubDynamicNoPIC ||
    419            PICStyle == PICStyles::StubPIC;
    420   }
    421 
    422   bool isCallingConvWin64(CallingConv::ID CC) const {
    423     return (isTargetWin64() && CC != CallingConv::X86_64_SysV) ||
    424            CC == CallingConv::X86_64_Win64;
    425   }
    426 
    427   /// ClassifyGlobalReference - Classify a global variable reference for the
    428   /// current subtarget according to how we should reference it in a non-pcrel
    429   /// context.
    430   unsigned char ClassifyGlobalReference(const GlobalValue *GV,
    431                                         const TargetMachine &TM)const;
    432 
    433   /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
    434   /// current subtarget according to how we should reference it in a non-pcrel
    435   /// context.
    436   unsigned char ClassifyBlockAddressReference() const;
    437 
    438   /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
    439   /// to immediate address.
    440   bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
    441 
    442   /// This function returns the name of a function which has an interface
    443   /// like the non-standard bzero function, if such a function exists on
    444   /// the current subtarget and it is considered prefereable over
    445   /// memset with zero passed as the second argument. Otherwise it
    446   /// returns null.
    447   const char *getBZeroEntry() const;
    448 
    449   /// This function returns true if the target has sincos() routine in its
    450   /// compiler runtime or math libraries.
    451   bool hasSinCos() const;
    452 
    453   /// Enable the MachineScheduler pass for all X86 subtargets.
    454   bool enableMachineScheduler() const override { return true; }
    455 
    456   /// enablePostRAScheduler - run for Atom optimization.
    457   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
    458                              TargetSubtargetInfo::AntiDepBreakMode& Mode,
    459                              RegClassVector& CriticalPathRCs) const override;
    460 
    461   bool postRAScheduler() const { return PostRAScheduler; }
    462 
    463   bool enableEarlyIfConversion() const override;
    464 
    465   /// getInstrItins = Return the instruction itineraries based on the
    466   /// subtarget selection.
    467   const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
    468 };
    469 
    470 } // End llvm namespace
    471 
    472 #endif
    473