| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 327 /// At first, the VSELECT condition is of vXi1 type. Later, targets may
328 /// change the condition type in order to match the VSELECT node using a
330 VSELECT,
[all...] |
| SelectionDAG.h | 703 return getNode(Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT,
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 82 setTargetDAGCombine(ISD::VSELECT);
100 setTargetDAGCombine(ISD::VSELECT);
272 setOperationAction(ISD::VSELECT, Ty, Legal);
317 setOperationAction(ISD::VSELECT, Ty, Legal);
657 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
773 // Transform the DAG into an equivalent VSELECT.
774 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
419 case ISD::VSELECT:
560 case ISD::VSELECT:
[all...] |
| SelectionDAGDumper.cpp | 195 case ISD::VSELECT: return "vselect";
|
| LegalizeVectorOps.cpp | 101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
265 case ISD::VSELECT:
648 case ISD::VSELECT:
665 // operands are vectors. Lower this select to VSELECT and implement it
843 // Implement VSELECT in terms of XOR, AND, OR
[all...] |
| LegalizeIntegerTypes.cpp | 70 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
526 return DAG.getNode(ISD::VSELECT, SDLoc(N),
[all...] |
| SelectionDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| BasicTargetTransformInfo.cpp | 463 ISD = ISD::VSELECT;
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 317 setOperationAction(ISD::VSELECT, VT, Expand);
353 setOperationAction(ISD::VSELECT, VT, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 468 setOperationAction(ISD::VSELECT, VT, Expand);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
[all...] |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 363 setTargetDAGCombine(ISD::VSELECT);
520 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 121 setOperationAction(ISD::VSELECT, VT, Expand);
[all...] |
