1 //===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the MIPS32/64 implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MipsSERegisterInfo.h" 16 #include "Mips.h" 17 #include "MipsAnalyzeImmediate.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSEInstrInfo.h" 20 #include "MipsSubtarget.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/IR/Constants.h" 28 #include "llvm/IR/DebugInfo.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/IR/Type.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/raw_ostream.h" 35 #include "llvm/Target/TargetFrameLowering.h" 36 #include "llvm/Target/TargetInstrInfo.h" 37 #include "llvm/Target/TargetMachine.h" 38 #include "llvm/Target/TargetOptions.h" 39 40 using namespace llvm; 41 42 #define DEBUG_TYPE "mips-reg-info" 43 44 MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST) 45 : MipsRegisterInfo(ST) {} 46 47 bool MipsSERegisterInfo:: 48 requiresRegisterScavenging(const MachineFunction &MF) const { 49 return true; 50 } 51 52 bool MipsSERegisterInfo:: 53 requiresFrameIndexScavenging(const MachineFunction &MF) const { 54 return true; 55 } 56 57 const TargetRegisterClass * 58 MipsSERegisterInfo::intRegClass(unsigned Size) const { 59 if (Size == 4) 60 return &Mips::GPR32RegClass; 61 62 assert(Size == 8); 63 return &Mips::GPR64RegClass; 64 } 65 66 /// Get the size of the offset supported by the given load/store. 67 /// The result includes the effects of any scale factors applied to the 68 /// instruction immediate. 69 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) { 70 switch (Opcode) { 71 case Mips::LD_B: 72 case Mips::ST_B: 73 return 10; 74 case Mips::LD_H: 75 case Mips::ST_H: 76 return 10 + 1 /* scale factor */; 77 case Mips::LD_W: 78 case Mips::ST_W: 79 return 10 + 2 /* scale factor */; 80 case Mips::LD_D: 81 case Mips::ST_D: 82 return 10 + 3 /* scale factor */; 83 default: 84 return 16; 85 } 86 } 87 88 /// Get the scale factor applied to the immediate in the given load/store. 89 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) { 90 switch (Opcode) { 91 case Mips::LD_H: 92 case Mips::ST_H: 93 return 2; 94 case Mips::LD_W: 95 case Mips::ST_W: 96 return 4; 97 case Mips::LD_D: 98 case Mips::ST_D: 99 return 8; 100 default: 101 return 1; 102 } 103 } 104 105 void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, 106 unsigned OpNo, int FrameIndex, 107 uint64_t StackSize, 108 int64_t SPOffset) const { 109 MachineInstr &MI = *II; 110 MachineFunction &MF = *MI.getParent()->getParent(); 111 MachineFrameInfo *MFI = MF.getFrameInfo(); 112 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 113 114 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 115 int MinCSFI = 0; 116 int MaxCSFI = -1; 117 118 if (CSI.size()) { 119 MinCSFI = CSI[0].getFrameIdx(); 120 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); 121 } 122 123 bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex); 124 125 // The following stack frame objects are always referenced relative to $sp: 126 // 1. Outgoing arguments. 127 // 2. Pointer to dynamically allocated stack space. 128 // 3. Locations for callee-saved registers. 129 // 4. Locations for eh data registers. 130 // Everything else is referenced relative to whatever register 131 // getFrameRegister() returns. 132 unsigned FrameReg; 133 134 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI) 135 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP; 136 else 137 FrameReg = getFrameRegister(MF); 138 139 // Calculate final offset. 140 // - There is no need to change the offset if the frame object is one of the 141 // following: an outgoing argument, pointer to a dynamically allocated 142 // stack space or a $gp restore location, 143 // - If the frame object is any of the following, its offset must be adjusted 144 // by adding the size of the stack: 145 // incoming argument, callee-saved register location or local variable. 146 bool IsKill = false; 147 int64_t Offset; 148 149 Offset = SPOffset + (int64_t)StackSize; 150 Offset += MI.getOperand(OpNo + 1).getImm(); 151 152 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); 153 154 if (!MI.isDebugValue()) { 155 // Make sure Offset fits within the field available. 156 // For MSA instructions, this is a 10-bit signed immediate (scaled by 157 // element size), otherwise it is a 16-bit signed immediate. 158 unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode()); 159 unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode()); 160 161 if (OffsetBitSize < 16 && isInt<16>(Offset) && 162 (!isIntN(OffsetBitSize, Offset) || 163 OffsetToAlignment(Offset, OffsetAlign) != 0)) { 164 // If we have an offset that needs to fit into a signed n-bit immediate 165 // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu 166 MachineBasicBlock &MBB = *MI.getParent(); 167 DebugLoc DL = II->getDebugLoc(); 168 unsigned ADDiu = Subtarget.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 169 const TargetRegisterClass *RC = 170 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; 171 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 172 unsigned Reg = RegInfo.createVirtualRegister(RC); 173 const MipsSEInstrInfo &TII = 174 *static_cast<const MipsSEInstrInfo *>( 175 MBB.getParent()->getTarget().getInstrInfo()); 176 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset); 177 178 FrameReg = Reg; 179 Offset = 0; 180 IsKill = true; 181 } else if (!isInt<16>(Offset)) { 182 // Otherwise split the offset into 16-bit pieces and add it in multiple 183 // instructions. 184 MachineBasicBlock &MBB = *MI.getParent(); 185 DebugLoc DL = II->getDebugLoc(); 186 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu; 187 unsigned NewImm = 0; 188 const MipsSEInstrInfo &TII = 189 *static_cast<const MipsSEInstrInfo *>( 190 MBB.getParent()->getTarget().getInstrInfo()); 191 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, 192 OffsetBitSize == 16 ? &NewImm : nullptr); 193 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg) 194 .addReg(Reg, RegState::Kill); 195 196 FrameReg = Reg; 197 Offset = SignExtend64<16>(NewImm); 198 IsKill = true; 199 } 200 } 201 202 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); 203 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset); 204 } 205