| /external/mesa3d/src/mesa/main/ |
| atifragshader.h | 24 GLenum opcode; member in struct:ati_fs_opcode_st
53 GLenum Opcode[2];
62 GLenum Opcode;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_program.h | 65 rc_presubtract_op Opcode;
82 * Opcode of this instruction, according to \ref rc_opcode enums.
84 unsigned int Opcode:8;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/tests/ |
| rc_test_helpers.c | 297 struct match_info Opcode;
334 tokens.Opcode.String = inst_str + matches[1].rm_so;
335 tokens.Opcode.Length = match_length(matches, 1);
347 if (strncmp(tokens.Opcode.String, info->Name, tokens.Opcode.Length)) {
350 inst->U.I.Opcode = info->Opcode;
|
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 151 unsigned Opcode;
155 MCInst() : Opcode(0) {}
157 void setOpcode(unsigned Op) { Opcode = Op; }
158 unsigned getOpcode() const { return Opcode; }
|
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 173 unsigned Opcode = BinOp->getOpcode();
220 else if (NextLevelBinOp->getOpcode() != Opcode)
242 unsigned &Opcode, Type *&Ty) {
284 Opcode = RdxStart->getOpcode();
305 unsigned &Opcode, Type *&Ty) {
375 Opcode = RdxOpcode;
|
| /external/llvm/lib/DebugInfo/ |
| DWARFDebugFrame.cpp | 61 /// opcode and an optional sequence of operands.
64 Instruction(uint8_t Opcode)
65 : Opcode(Opcode)
68 uint8_t Opcode;
74 /// Convenience methods to add a new instruction with the given opcode and
76 void addInstruction(uint8_t Opcode) {
77 Instructions.push_back(Instruction(Opcode));
80 void addInstruction(uint8_t Opcode, uint64_t Operand1) {
81 Instructions.push_back(Instruction(Opcode));
[all...] |
| /external/llvm/lib/IR/ |
| Instruction.cpp | 190 const char *Instruction::getOpcodeName(unsigned OpCode) {
191 switch (OpCode) {
339 // We have two instructions of identical opcode and #operands. Check to see
368 // We have two instructions of identical opcode and #operands. Check to see
459 bool Instruction::isAssociative(unsigned Opcode) {
460 return Opcode == And || Opcode == Or || Opcode == Xor ||
461 Opcode == Add || Opcode == Mul
[all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 191 unsigned Opcode = MCID.getOpcode();
192 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
199 static bool isFpMulInstruction(unsigned Opcode) {
200 switch (Opcode) {
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 338 unsigned Opcode = 0;
341 Opcode = MSP430::MOV8rm_POST;
344 Opcode = MSP430::MOV16rm_POST;
350 return CurDAG->getMachineNode(Opcode, SDLoc(N),
|
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 54 unsigned Opcode = Mips::Mflo16;
55 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
59 unsigned Opcode = Mips::Mfhi16;
60 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
243 unsigned Opcode = Node->getOpcode();
253 switch(Opcode) {
265 if (Opcode == ISD::ADDE) {
294 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
308 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 222 unsigned Opcode;
270 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
271 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
272 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
273 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
274 case Intrinsic::rint: Opcode = ISD::FRINT; break;
275 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
276 case Intrinsic::round: Opcode = ISD::FROUND; break;
311 Opcode = ISD::FSQRT; break;
315 Opcode = ISD::FFLOOR; break
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 295 int Opcode = SU->getInstr()->getOpcode();
297 if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode))
300 if (TII->isALUInstr(Opcode)) {
304 switch (Opcode) {
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 178 unsigned Opcode = I->getOpcode();
179 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
180 return true; // Unknown Opcode.
206 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 168 unsigned Opcode = MI->getOpcode();
170 if (Opcode == SystemZ::AHI)
172 else if (Opcode == SystemZ::AGHI)
215 unsigned Opcode = TII->getLoadAndTest(MI->getOpcode());
216 if (!Opcode)
219 MI->setDesc(TII->get(Opcode));
233 int Opcode = MI->getOpcode();
234 const MCInstrDesc &Desc = TII->get(Opcode);
|
| SystemZFrameLowering.cpp | 288 unsigned Opcode;
291 Opcode = SystemZ::AGHI;
293 Opcode = SystemZ::AGFI;
302 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
420 unsigned Opcode = MBBI->getOpcode();
421 if (Opcode != SystemZ::LMG)
427 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
436 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 47 const char *llvm::X86Disassembler::GetInstrName(unsigned Opcode,
50 return MII->getName(Opcode);
323 uint32_t Opcode = mcInst.getOpcode();
330 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
331 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
332 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
333 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &
[all...] |
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 291 unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
292 switch (Opcode) {
454 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
456 switch (Opcode) {
683 unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
684 switch (Opcode) {
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 65 int Opcode = MI->getOpcode();
66 if (Opcode == XCore::LDWFI)
87 int Opcode = MI->getOpcode();
88 if (Opcode == XCore::STWFI)
136 /// the correspondent Branch instruction opcode.
149 /// opcode that matches the cc.
414 /// ReverseBranchCondition - Return the inverse opcode of the
452 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
453 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value);
|
| /external/llvm/lib/Transforms/Utils/ |
| BypassSlowDivision.cpp | 232 unsigned Opcode = J->getOpcode();
233 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv;
234 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem;
235 bool UseSignedOp = Opcode == Instruction::SDiv ||
236 Opcode == Instruction::SRem;
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_program.h | 65 rc_presubtract_op Opcode;
82 * Opcode of this instruction, according to \ref rc_opcode enums.
84 unsigned int Opcode:8;
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| rc_test_helpers.c | 297 struct match_info Opcode;
334 tokens.Opcode.String = inst_str + matches[1].rm_so;
335 tokens.Opcode.Length = match_length(matches, 1);
347 if (strncmp(tokens.Opcode.String, info->Name, tokens.Opcode.Length)) {
350 inst->U.I.Opcode = info->Opcode;
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| evntprov.h | 61 UCHAR Opcode;
194 UCHAR Opcode,
202 EventDescriptor->Opcode = Opcode;
243 return (EventDescriptor->Opcode);
304 UCHAR Opcode)
306 EventDescriptor->Opcode = Opcode;
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| IvarInvalidationChecker.cpp | 677 BinaryOperatorKind Opcode = BO->getOpcode();
678 if (Opcode != BO_Assign &&
679 Opcode != BO_EQ &&
680 Opcode != BO_NE)
688 if (Opcode != BO_Assign && isZero(BO->getLHS())) {
|
| /external/llvm/lib/MC/MCAnalysis/ |
| MCModuleYAML.cpp | 31 // This class is used to map opcode and register names to enum values.
94 OpcodeEnum Opcode;
193 IO.mapRequired("Inst", I.Opcode);
269 return "Invalid instruction opcode.";
320 A.Insts[i].Opcode = MCDI.Inst.getOpcode();
380 MI.setOpcode(II->Opcode);
|
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 240 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
256 Inst.setOpcode(Opcode);
290 unsigned Opcode) {
335 Inst.setOpcode(Opcode);
423 default: llvm_unreachable("Invalid opcode");
447 default: llvm_unreachable("Invalid opcode");
462 unsigned Opcode = OutMI.getOpcode();
465 OutMI.setOpcode(Opcode);
481 unsigned Opcode;
483 default: llvm_unreachable("Invalid opcode");
[all...] |
