| /prebuilts/ndk/9/platforms/android-16/arch-x86/usr/include/asm/ |
| voyager.h | 421 struct voyager_psi_subregs subregs; member in struct:voyager_psi
|
| /prebuilts/ndk/9/platforms/android-17/arch-x86/usr/include/asm/ |
| voyager.h | 421 struct voyager_psi_subregs subregs; member in struct:voyager_psi
|
| /prebuilts/ndk/9/platforms/android-18/arch-x86/usr/include/asm/ |
| voyager.h | 421 struct voyager_psi_subregs subregs; member in struct:voyager_psi
|
| /prebuilts/ndk/9/platforms/android-19/arch-x86/usr/include/asm/ |
| voyager.h | 421 struct voyager_psi_subregs subregs; member in struct:voyager_psi
|
| /prebuilts/ndk/9/platforms/android-9/arch-x86/usr/include/asm/ |
| voyager.h | 421 struct voyager_psi_subregs subregs; member in struct:voyager_psi
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 216 /// loads of D registers and even subregs and odd subregs of Q registers.
224 /// stores of D registers and even subregs and odd subregs of Q registers.
[all...] |
| ARMAsmPrinter.cpp | 136 assert(!MO.getSubReg() && "Subregs should be eliminated!");
[all...] |
| ARMISelLowering.cpp | 438 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
[all...] |
| ARMInstrNEON.td | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 138 unsigned SubRegs[]);
834 static unsigned SubRegs[] = { AArch64::dsub0, AArch64::dsub1,
837 return createTuple(Regs, RegClassIDs, SubRegs);
843 static unsigned SubRegs[] = { AArch64::qsub0, AArch64::qsub1,
846 return createTuple(Regs, RegClassIDs, SubRegs);
851 unsigned SubRegs[]) {
870 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], MVT::i32));
[all...] |
| AArch64AsmPrinter.cpp | 218 assert(!MO.getSubReg() && "Subregs should be eliminated!");
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 499 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
500 /// ssub_0:S0 - ssub_3:S3 subregs.
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineCSE.cpp | 145 // The 2-addr pass has been updated to handle coalesced subregs. However,
|
| PeepholeOptimizer.cpp | 848 // Def.sub0 (i.e, not defining the other subregs) and we would
[all...] |
| RegAllocFast.cpp | 665 // subregs. This may invalidate any operand pointers.
[all...] |
| InlineSpiller.cpp | [all...] |
| RegisterCoalescer.cpp | 321 // FIXME: Coalescer should support subregs symmetrically.
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| coalesce-subregs.ll | 121 ; The destination lane isn't read, so the subregs can coalesce.
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| cfgloop.h | 331 due to need to handle subregs and extends. The value of the object described
|
| rtl.h | [all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.td | [all...] |
| SystemZISelLowering.cpp | 212 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrCompiler.td | [all...] |
| /prebuilts/clang/linux-x86/host/3.4/bin/ |
| tblgen | |
