| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 76 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
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| /external/llvm/test/CodeGen/X86/ |
| misched-new.ll | 58 ; Test that the DAG builder can handle an undef vreg on ExitSU.
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| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 291 // Find the original register that VReg is copied from.
292 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
293 while (TargetRegisterInfo::isVirtualRegister(VReg)) {
294 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
296 return VReg;
297 VReg = DefMI->getOperand(1).getReg();
299 return VReg;
302 // Determine if VReg is defined by an instruction that can be folded into a
305 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
307 VReg = removeCopies(MRI, VReg)
[all...] |
| AArch64CallingConvention.td | 198 // vreg on entry, use it in RET & tail call generation; make that vreg def if we
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| AArch64RegisterInfo.td | 44 def vreg : RegAltNameIndex;
315 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in {
350 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
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| /external/llvm/include/llvm/CodeGen/ |
| MachineRegisterInfo.h | 29 /// registers, including vreg register classes, use/def chains for registers,
56 /// Each element in this list contains the register class of the vreg and the
739 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
740 LiveIns.push_back(std::make_pair(Reg, vreg));
753 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
755 unsigned getLiveInPhysReg(unsigned VReg) const;
[all...] |
| FastISel.h | 134 /// \brief The specified machine instr operand is a vreg, and that vreg is
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| LiveRangeEdit.h | 102 void MRI_NoteNewVirtualRegister(unsigned VReg) override;
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| FunctionLoweringInfo.h | 63 /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
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| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /art/compiler/dex/quick/ |
| gen_loadstore.cc | 47 // Now, determine if this vreg is ever used as a reference. If not, we're done.
279 * If src reg[s] are tied to the original Dalvik vreg via liveness or promotion, we
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| ralloc_util.cc | 210 * Break the association between a Dalvik vreg and a physical temp register of either register
215 * of Dalvik vregs. This can result in useless register copies when the same Dalvik vreg
[all...] |
| /art/runtime/gc/collector/ |
| mark_sweep.cc | 474 void MarkSweep::VerifyRootCallback(const Object* root, void* arg, size_t vreg,
476 reinterpret_cast<MarkSweep*>(arg)->VerifyRoot(root, vreg, visitor, root_type);
479 void MarkSweep::VerifyRoot(const Object* root, size_t vreg, const StackVisitor* visitor,
487 LOG(ERROR) << visitor->DescribeLocation() << " in VReg: " << vreg;
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_x86_defs.c | [all...] |
| /external/chromium_org/v8/src/mips/ |
| lithium-mips.cc | 626 int vreg = allocator_->GetVirtualRegister(); local
629 vreg = 0;
631 operand->set_virtual_register(vreg);
639 int vreg = allocator_->GetVirtualRegister(); local
642 vreg = 0;
644 operand->set_virtual_register(vreg);
[all...] |
| /external/llvm/lib/CodeGen/ |
| InlineSpiller.cpp | 184 void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI);
185 void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI);
[all...] |
| ScheduleDAGInstrs.cpp | 386 // Add output dependence to the next nearest def of this vreg.
418 // Record this local VReg use.
428 assert(LIS && "vreg dependencies requires LiveIntervals");
454 // Add antidependence to the following def of the vreg it uses.
834 // for vreg defs with no in-region use, and prefetches with no vreg def.
[all...] |
| LiveVariables.cpp | 84 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
701 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
799 // Record all vreg defs and kills of all instructions in SuccBB.
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| MachineScheduler.cpp | 873 // For each live out vreg reduce the pressure change associated with other
874 // uses of the same vreg below the live-out reaching def.
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 875 unsigned VReg =
877 RegInfo.addLiveIn(VA.getLocReg(), VReg);
878 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
880 unsigned VReg =
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 524 // destination vreg to set, the condition code register to branch on, the
586 // destination vreg to set, the condition code register to branch on, the
650 // destination vreg to set, the condition code register to branch on, the
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 254 return print_reg_class('VReg', 'VGPR', $reg_width, $VGPR_COUNT, $sub_reg_ref, @types);
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_wm_pass2.c | 242 dst[i] = &c->vreg[c->nr_vreg++];
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| /external/llvm/lib/Transforms/Scalar/ |
| Sink.cpp | 80 // the definition of the vreg. Dwarf generator handles this although the
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 254 return print_reg_class('VReg', 'VGPR', $reg_width, $VGPR_COUNT, $sub_reg_ref, @types);
|
