| /external/chromium_org/third_party/skia/include/core/ |
| SkChecksum.h | 30 ROTL = sizeof(uintptr_t) * 8 - ROTR,
35 return ((total >> ROTR) | (total << ROTL)) ^ value;
|
| /external/skia/include/core/ |
| SkChecksum.h | 30 ROTL = sizeof(uintptr_t) * 8 - ROTR,
35 return ((total >> ROTR) | (total << ROTL)) ^ value;
|
| /external/chromium_org/net/http/ |
| md4.cc | 65 #define ROTL(x,n) (((x) << (n)) | ((x) >> (0x20 - n)))
68 #define RD1(a,b,c,d,k,s) a += F(b,c,d) + X[k]; a = ROTL(a,s)
71 #define RD2(a,b,c,d,k,s) a += G(b,c,d) + X[k] + 0x5A827999; a = ROTL(a,s)
74 #define RD3(a,b,c,d,k,s) a += H(b,c,d) + X[k] + 0x6ED9EBA1; a = ROTL(a,s)
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZSelectionDAGInfo.cpp | 186 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
188 return ROTL;
|
| SystemZISelDAGToDAG.cpp | 106 // (or (rotl Input, Rotate), ~Mask)
110 // (and (rotl Input, Rotate), Mask)
750 case ISD::ROTL: {
802 // Treat (shl X, count) as (rotl X, size-count) as long as the bottom
807 // Treat (shl X, count) as (and (rotl X, count), ~0<<count).
829 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
834 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 311 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 43 setOperationAction(ISD::ROTL, MVT::i32, Custom);
250 case ISD::ROTL: return LowerROTL(Op, DAG);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 43 setOperationAction(ISD::ROTL, MVT::i32, Custom);
250 case ISD::ROTL: return LowerROTL(Op, DAG);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 180 case ISD::ROTL: return "rotl";
|
| LegalizeVectorOps.cpp | 256 case ISD::ROTL:
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 165 setOperationAction(ISD::ROTL, MVT::i64, Legal);
168 setOperationAction(ISD::ROTL, MVT::i64, Expand);
172 setOperationAction(ISD::ROTL, MVT::i32, Legal);
175 setOperationAction(ISD::ROTL, MVT::i32, Expand);
179 setOperationAction(ISD::ROTL, MVT::i16, Expand);
181 setOperationAction(ISD::ROTL, MVT::i8, Expand);
[all...] |
| /external/chromium_org/third_party/openssl/openssl/crypto/bn/asm/ |
| ppc.pl | 126 $ROTL= "rotlwi"; # rotate left by immediate
150 $ROTL= "rotldi"; # rotate left by immediate
[all...] |
| /external/openssl/crypto/bn/asm/ |
| ppc.pl | 126 $ROTL= "rotlwi"; # rotate left by immediate
150 $ROTL= "rotldi"; # rotate left by immediate
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 98 setOperationAction(ISD::ROTL, MVT::i8, Expand);
100 setOperationAction(ISD::ROTL, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 397 } else if (Opcode == ISD::ROTL) {
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 269 // The hardware supports 32-bit ROTR, but not ROTL.
270 setOperationAction(ISD::ROTL, MVT::i32, Expand);
271 setOperationAction(ISD::ROTL, MVT::i64, Expand);
298 setOperationAction(ISD::ROTL, VT, Expand);
[all...] |
| /external/valgrind/main/VEX/priv/ |
| guest_ppc_toIR.c | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 113 setOperationAction(ISD::ROTL , MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 315 setOperationAction(ISD::ROTL, MVT::i32, Expand);
316 setOperationAction(ISD::ROTL, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 231 setOperationAction(ISD::ROTL, MVT::i32, Expand);
232 setOperationAction(ISD::ROTL, MVT::i64, Expand);
[all...] |
