/external/llvm/lib/CodeGen/ |
LocalStackSlotAllocation.cpp | 391 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF);
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MachineSSAUpdater.cpp | 116 const TargetRegisterClass *RC,
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MachineVerifier.cpp | [all...] |
RegAllocGreedy.cpp | 817 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg); [all...] |
MachineLICM.cpp | 786 const TargetRegisterClass *RC = MRI->getRegClass(Reg); [all...] |
RegisterCoalescer.cpp | 290 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); 291 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); 778 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); 825 const TargetRegisterClass *NewRC = CP.getNewRC(); [all...] |
MachineFunction.cpp | 436 const TargetRegisterClass *RC) { 440 const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg); [all...] |
TailDuplication.cpp | 404 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); 441 const TargetRegisterClass *RC = MRI->getRegClass(Reg); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonHardwareLoops.cpp | 766 const TargetRegisterClass *RC = MRI->getRegClass(R); 771 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass; [all...] |
HexagonPeephole.cpp | 250 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
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/external/llvm/lib/Target/NVPTX/ |
NVPTXAsmPrinter.h | 258 typedef DenseMap<const TargetRegisterClass *, VRegMap> VRegRCMap;
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/external/llvm/lib/Target/Mips/ |
MipsSEInstrInfo.cpp | 185 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 227 unsigned DestReg, int FI, const TargetRegisterClass *RC, 388 const TargetRegisterClass *RC = STI.isABI_N64() ?
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MipsISelLowering.cpp | [all...] |
MipsSEISelLowering.cpp | 233 const TargetRegisterClass * 243 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 292 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreFrameLowering.cpp | 432 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 460 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 568 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
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/external/llvm/lib/Target/PowerPC/ |
PPCFrameLowering.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGRRList.cpp | 232 const TargetRegisterClass*, 233 const TargetRegisterClass*, 292 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); 301 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 309 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); [all...] |
TargetLowering.cpp | [all...] |
/external/llvm/lib/Target/R600/ |
SIISelLowering.cpp | 424 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); [all...] |
R600MachineScheduler.cpp | 212 const TargetRegisterClass *RC) const {
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/external/llvm/lib/Target/SystemZ/ |
SystemZInstrInfo.cpp | 593 const TargetRegisterClass *RC, 609 const TargetRegisterClass *RC, [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
AMDGPUISelLowering.cpp | 314 const TargetRegisterClass *RC,
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/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.h | 437 std::pair<unsigned, const TargetRegisterClass *>
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AArch64InstrInfo.cpp | 375 const TargetRegisterClass *RC = 495 const TargetRegisterClass *RC = nullptr; 629 const TargetRegisterClass *OpRegCstraints = [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
AMDGPUISelLowering.cpp | 314 const TargetRegisterClass *RC,
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