| /external/llvm/lib/Target/Hexagon/ |
| HexagonMCInstLower.cpp | 93 MCI.addOperand(MCO);
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| HexagonPeephole.cpp | 224 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
231 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
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| /external/llvm/lib/Target/MSP430/ |
| MSP430MCInstLower.cpp | 155 OutMI.addOperand(MCOp);
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| MSP430BranchSelector.cpp | 157 .addImm(4).addOperand(Cond[0]);
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| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 121 TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg));
125 TmpInst0.addOperand(MCOp);
719 I.addOperand(
727 I.addOperand(MCOperand::CreateReg(Reg));
745 I.addOperand(MCOperand::CreateReg(Reg1));
746 I.addOperand(MCOperand::CreateReg(Reg2));
754 I.addOperand(MCOperand::CreateReg(Reg1));
755 I.addOperand(MCOperand::CreateReg(Reg2));
756 I.addOperand(MCOperand::CreateReg(Reg3));
[all...] |
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 110 Inst.addOperand(MCOperand::CreateImm(0));
112 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
114 Inst.addOperand(MCOperand::CreateExpr(Expr));
232 Inst.addOperand(MCOperand::CreateReg(getReg()));
237 Inst.addOperand(MCOperand::CreateImm(AccessReg));
246 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
252 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
254 Inst.addOperand(MCOperand::CreateReg(Mem.Index));
259 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
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| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 220 Inst.addOperand(MCOperand::CreateReg(Reg));
232 Inst.addOperand(MCOperand::CreateReg(Reg));
243 Inst.addOperand(MCOperand::CreateImm(Values[Val]));
249 Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val));
378 Inst.addOperand(MCOperand::CreateImm(Op1));
419 Inst.addOperand(MCOperand::CreateImm(Op2));
568 Inst.addOperand(MCOperand::CreateImm(Op1));
583 Inst.addOperand(MCOperand::CreateImm(Op3));
639 Inst.addOperand(MCOperand::CreateImm(Op3));
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| /external/llvm/lib/Target/XCore/ |
| XCoreMCInstLower.cpp | 115 OutMI.addOperand(MCOp);
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| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 208 NewMI.addOperand(MI->getOperand(i));
272 .addOperand(MI->getOperand(0))
273 .addOperand(MI->getOperand(1))
317 .addOperand(MI->getOperand(3))
329 .addOperand(RID)
330 .addOperand(SID)
336 .addOperand(MI->getOperand(2))
348 .addOperand(RID)
349 .addOperand(SID)
355 .addOperand(MI->getOperand(0)
[all...] |
| AMDGPUMCInstLower.cpp | 81 OutMI.addOperand(MCOp);
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| SILowerControlFlow.cpp | 141 .addOperand(To)
270 .addOperand(MI.getOperand(1))
318 .addOperand(Op);
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| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 187 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
216 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
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| Thumb2InstrInfo.cpp | 39 NopInst.addOperand(MCOperand::CreateImm(0));
40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
41 NopInst.addOperand(MCOperand::CreateReg(0));
481 MI.addOperand(MachineOperand::CreateReg(0, false));
512 MI.addOperand(MachineOperand::CreateReg(0, false));
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 253 Inst.addOperand(MCOperand::CreateReg(getReg()));
265 Inst.addOperand(MCOperand::CreateImm(0));
267 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
269 Inst.addOperand(MCOperand::CreateExpr(Expr));
275 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
278 Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
284 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
|
| /external/chromium_org/third_party/skia/src/pathops/ |
| SkOpEdgeBuilder.cpp | 20 void SkOpEdgeBuilder::addOperand(const SkPath& path) {
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| /external/llvm/include/llvm/MC/ |
| MCInst.h | 167 void addOperand(const MCOperand &Op) {
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| /external/llvm/lib/MC/ |
| MCExternalSymbolizer.cpp | 139 MI.addOperand(MCOperand::CreateExpr(Expr));
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| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionalCompares.cpp | 600 .addOperand(HeadCond[2])
658 .addOperand(CmpMI->getOperand(FirstOp)); // Register Rn
662 MIB.addOperand(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate
672 .addOperand(CmpMI->getOperand(1)); // Branch target.
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| AArch64BranchRelaxation.cpp | 432 .addOperand(MI->getOperand(0));
435 MIB.addOperand(MI->getOperand(1));
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| /external/llvm/lib/Transforms/Utils/ |
| CloneModule.cpp | 120 NewNMD->addOperand(MapValue(NMD.getOperand(i), VMap));
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| /external/skia/src/pathops/ |
| SkOpEdgeBuilder.cpp | 20 void SkOpEdgeBuilder::addOperand(const SkPath& path) {
|
| /external/llvm/lib/CodeGen/ |
| MachineInstr.cpp | 540 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
543 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
577 addOperand(MF, MI.getOperand(i));
610 void MachineInstr::addOperand(const MachineOperand &Op) {
615 addOperand(*MF, Op);
635 /// addOperand - Add the specified operand to the instruction. If it is an
639 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
644 // This is unusual: MI->addOperand(MI->getOperand(i)).
648 return addOperand(MF, CopyOp);
[all...] |
| LiveVariables.cpp | 247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
|
| /external/llvm/lib/IR/ |
| Module.cpp | 317 getOrInsertModuleFlagsMetadata()->addOperand(MDNode::get(Context, Ops));
330 getOrInsertModuleFlagsMetadata()->addOperand(Node);
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 708 .addOperand(Dest);
713 MIB.addOperand(MI->getOperand(I));
737 .addOperand(Dest).addReg(0)
794 .addOperand(MI->getOperand(1)).addFrameIndex(FrameIndex)
827 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
833 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
853 MIB.addOperand(MI->getOperand(I));
[all...] |
