| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 421 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
422 MemOp[0] = LD->getMemOperand();
423 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
458 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
459 MemOp[0] = LD->getMemOperand();
460 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
482 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
483 MemOp[0] = LD->getMemOperand()
[all...] |
| HexagonSubtarget.cpp | 36 "Generate V4 MEMOP in code generation for Hexagon target"));
43 "Do not generate V4 MEMOP in code generation for Hexagon target"));
|
| HexagonScheduleV4.td | 17 // | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
|
| HexagonInstrInfoV4.td | 36 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
73 // MEMOP Instructions:
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrXOP.td | 14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
20 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
41 Operand memop, ComplexPattern mem_cpat> {
45 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
56 PatFrag memop> {
62 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
69 PatFrag memop> {
75 [(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L;
|
| X86InstrFragmentsSIMD.td | 399 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
414 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
415 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
417 // 128-bit memop pattern fragments
419 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
420 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
421 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
423 // 256-bit memop pattern fragments
425 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
426 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>
[all...] |
| X86InstrFMA.td | 156 X86MemOperand x86memop, Operand memop, PatFrag mem_frag,
250 multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop,
261 (ins VR128:$src1, VR128:$src2, memop:$src3),
267 (ins VR128:$src1, memop:$src2, VR128:$src3),
|
| X86ISelDAGToDAG.cpp | [all...] |
| X86InstrInfo.cpp | 69 // Do not insert the reverse map (MemOp -> RegOp) into the table.
73 // Do not insert the forward map (RegOp -> MemOp) into the table.
82 // Used for RegOp->MemOp conversion.
94 uint16_t MemOp;
276 unsigned MemOp = OpTbl2Addr[i].MemOp;
279 RegOp, MemOp,
385 unsigned MemOp = OpTbl0[i].MemOp;
388 RegOp, MemOp, TB_INDEX_0 | Flags)
[all...] |
| X86InstrMMX.td | 535 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
541 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
|
| X86InstrInfo.h | 164 unsigned RegOp, unsigned MemOp, unsigned Flags);
|
| /external/chromium_org/v8/src/arm/ |
| disasm-arm.cc | 522 if (format[1] == 'e') { // 'memop: load/store instructions.
523 ASSERT(STRING_STARTS_WITH(format, "memop"));
746 Format(instr, "'memop'cond's 'rd, ['rn], -'rm");
748 Format(instr, "'memop'cond's 'rd, ['rn], #-'off8");
754 Format(instr, "'memop'cond's 'rd, ['rn], +'rm");
756 Format(instr, "'memop'cond's 'rd, ['rn], #+'off8");
762 Format(instr, "'memop'cond's 'rd, ['rn, -'rm]'w");
764 Format(instr, "'memop'cond's 'rd, ['rn, #-'off8]'w");
770 Format(instr, "'memop'cond's 'rd, ['rn, +'rm]'w");
772 Format(instr, "'memop'cond's 'rd, ['rn, #+'off8]'w")
[all...] |
| simulator-arm.cc | [all...] |
| /external/qemu/tcg/ |
| tcg.c | 859 void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
861 memop = tcg_canonicalize_memop(memop, 0, 0);
867 *tcg_ctx.gen_opparam_ptr++ = memop;
873 assert((memop & MO_BSWAP) == MO_TE || (memop & MO_SIZE) == MO_8);
874 assert(old_ld_opc[memop & MO_SSIZE] != 0);
877 *tcg_ctx.gen_opc_ptr++ = old_ld_opc[memop & MO_SSIZE];
884 *tcg_ctx.gen_opc_ptr++ = old_ld_opc[memop & MO_SSIZE];
894 void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
936 tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); local
971 tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); local
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 155 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
156 MemOp[0] = MF->getMachineMemOperand(
158 cast<MachineSDNode>(node)->setMemRefs(MemOp, MemOp + 1);
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 85 X86Operand &MemOp = static_cast<X86Operand &>(Op);
87 if (IsStackReg(MemOp.getMemBaseReg()) || IsStackReg(MemOp.getMemIndexReg()))
92 InstrumentMemOperandSmallImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
94 InstrumentMemOperandLargeImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
|
| X86Operand.h | 49 struct MemOp {
62 struct MemOp Mem;
|
| /external/vixl/src/a64/ |
| assembler-a64.cc | 1054 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | local
1069 Emit(addrmodeop | memop);
1841 Instr memop = op | Rt(rt) | RnSP(addr.base()); local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /external/qemu/tcg/i386/ |
| tcg-target.c | [all...] |
| /external/chromium_org/v8/src/arm64/ |
| assembler-arm64.cc | 1378 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | local
2209 Instr memop = op | Rt(rt) | RnSP(addr.base()); local
[all...] |
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 90 struct MemOp {
104 MemOp Mem;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 636 SDValue MemOp;
641 MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
648 MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
652 MemOpChains.push_back(MemOp);
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 166 struct MemOp {
176 struct MemOp Mem;
|
