/external/llvm/test/TableGen/ |
MultiPat.td | 73 def REGCLASS : RegisterClass<[], []>; 98 !subst(REGCLASS, VR128, 103 !subst(REGCLASS, VR128, 116 [[(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))], 117 [(set REGCLASS:$dst, (bitconvert (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))), 118 (MNEMONIC REGCLASS:$dst, REGCLASS:$src)]]> [all...] |
TargetInstrSpec.td | 70 def REGCLASS : RegisterClass<[], []>; 91 !subst(REGCLASS, VR128, Decls.operand))))>; 98 !subst(REGCLASS, VR128, Decls.operand))))>; 102 [(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))]>;
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/external/llvm/lib/Target/NVPTX/ |
NVPTXInstrInfo.td | [all...] |
NVPTXVector.td | 241 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass, 243 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a, regclass:$b), 245 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))], 255 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass, 257 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a) [all...] |
NVPTXIntrinsics.td | [all...] |
/development/ndk/sources/android/libportable/arch-arm/ |
unwind.c | 44 _Unwind_VRS_RegClass regclass, 50 _Unwind_VRS_RegClass regclass,
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
SIMCCodeEmitter.cpp | 79 unsigned RegClass = Desc.OpInfo[OpNo].RegClass; 80 return (AMDGPU::SSrc_32RegClassID == RegClass) || 81 (AMDGPU::SSrc_64RegClassID == RegClass) || 82 (AMDGPU::VSrc_32RegClassID == RegClass) || 83 (AMDGPU::VSrc_64RegClassID == RegClass);
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/ndk/sources/cxx-stl/llvm-libc++abi/libcxxabi/src/Unwind/ |
Unwind-EHABI.cpp | 744 _Unwind_VRS_RegClass regclass, 748 _LIBUNWIND_TRACE_API("_Unwind_VRS_Set(context=%p, regclass=%d, reg=%d, " 749 "rep=%d, value=0x%llX)\n", context, regclass, 753 switch (regclass) { 796 _Unwind_VRS_RegClass regclass, 801 switch (regclass) { 844 _Unwind_VRS_RegClass regclass, 849 _Unwind_VRS_Get_Internal(context, regclass, regno, representation, 851 _LIBUNWIND_TRACE_API("_Unwind_VRS_Get(context=%p, regclass=%d, reg=%d, " 853 context, regclass, regno, representation [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrArithmetic.td | 601 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass, 614 /// RegClass - This is the register class associated with this type. For 616 RegisterClass RegClass = regclass; [all...] |
/external/libcxxabi/src/Unwind/ |
Unwind-EHABI.cpp | 778 _Unwind_VRS_RegClass regclass, 782 _LIBUNWIND_TRACE_API("_Unwind_VRS_Set(context=%p, regclass=%d, reg=%d, " 783 "rep=%d, value=0x%llX)\n", context, regclass, 787 switch (regclass) { 830 _Unwind_VRS_RegClass regclass, 835 switch (regclass) { 878 _Unwind_VRS_RegClass regclass, 883 _Unwind_VRS_Get_Internal(context, regclass, regno, representation, 885 _LIBUNWIND_TRACE_API("_Unwind_VRS_Get(context=%p, regclass=%d, reg=%d, " 887 context, regclass, regno, representation [all...] |
/external/llvm/lib/Target/R600/ |
SIISelLowering.cpp | [all...] |
SIISelLowering.h | 38 unsigned RegClass) const; 40 unsigned RegClass, bool &ScalarSlotUsed) const;
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SIInstrInfo.td | 471 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A < 473 (outs regClass:$vdst), 483 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS < 485 (outs regClass:$vdst), 495 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A < 498 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset), 507 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A < 510 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u8imm:$offset0, u8imm:$offset1), 566 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF < 569 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc [all...] |
/ndk/sources/cxx-stl/gabi++/include/ |
unwind-arm.h | 123 _Unwind_VRS_RegClass regclass, 129 _Unwind_VRS_RegClass regclass,
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/prebuilts/ndk/9/sources/cxx-stl/EH/gabi++/include/ |
unwind-arm.h | 124 _Unwind_VRS_RegClass regclass, 130 _Unwind_VRS_RegClass regclass,
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/prebuilts/ndk/9/sources/cxx-stl/llvm-libc++/gabi++/include/ |
unwind-arm.h | 124 _Unwind_VRS_RegClass regclass, 130 _Unwind_VRS_RegClass regclass,
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/external/llvm/include/llvm/CodeGen/ |
RegisterScavenging.h | 125 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const; 154 unsigned scavengeRegister(const TargetRegisterClass *RegClass, 156 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { 157 return scavengeRegister(RegClass, MBBI, SPAdj);
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/external/llvm/lib/CodeGen/ |
MachineRegisterInfo.cpp | 97 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 98 assert(RegClass && "Cannot create register without RegClass!"); 99 assert(RegClass->isAllocatable() && 100 "Virtual register RegClass must be allocatable."); 105 VRegInfo[Reg].first = RegClass;
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RegisterClassInfo.cpp | 43 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 80 RCInfo &RCI = RegClass[RC->getID()]; 116 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
AMDILUtilityFunctions.h | 66 // These macros expand to common groupings of RegClass ID's
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/external/mesa3d/src/gallium/drivers/radeon/ |
AMDILUtilityFunctions.h | 66 // These macros expand to common groupings of RegClass ID's
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/prebuilts/ndk/4/platforms/android-3/arch-arm/usr/lib/ |
libdl.so | |
/prebuilts/ndk/4/platforms/android-4/arch-arm/usr/lib/ |
libdl.so | |
/prebuilts/ndk/4/platforms/android-5/arch-arm/usr/lib/ |
libdl.so | |
/prebuilts/ndk/4/platforms/android-8/arch-arm/usr/lib/ |
libdl.so | |