| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 260 SDLoc dl(GA);
263 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
268 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
270 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
290 SDLoc DL(GN);
295 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset);
300 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);
311 return DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), CP,
319 SDLoc DL(Op);
324 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result)
1035 SDLoc &dl = CLI.DL; local
1545 DebugLoc dl = MI->getDebugLoc(); local
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCalls.cpp | 61 unsigned DstAlign = getKnownAlignment(MI->getArgOperand(0), DL);
62 unsigned SrcAlign = getKnownAlignment(MI->getArgOperand(1), DL);
108 if (DL && SrcETy->isSized() && DL->getTypeStoreSize(SrcETy) == Size) {
157 unsigned Alignment = getKnownAlignment(MI->getDest(), DL);
279 if (getObjectSize(II->getArgOperand(0), Size, DL, TLI))
524 if (getOrEnforceKnownAlignment(II->getArgOperand(0), 16, DL) >= 16) {
533 if (getOrEnforceKnownAlignment(II->getArgOperand(1), 16, DL) >= 16) {
544 if (getOrEnforceKnownAlignment(II->getArgOperand(0), 16, DL) >= 16) {
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 37 MachineBasicBlock::iterator MI, DebugLoc DL,
95 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
101 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
123 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
161 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
194 DebugLoc DL = MBB.findDebugLoc(MI);
200 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
206 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), TgtReg)
231 BuildMI(MBB, MI, DL, get(Opcode), MFI->SpillTracker.LaneVGPR)
246 DebugLoc DL = MBB.findDebugLoc(MI)
[all...] |
| AMDGPUISelDAGToDAG.cpp | 657 SDLoc DL(N);
667 DL, MVT::i32, LHS, Sub0);
669 DL, MVT::i32, LHS, Sub1);
672 DL, MVT::i32, RHS, Sub0);
674 DL, MVT::i32, RHS, Sub1);
688 SDNode *AddLo = CurDAG->getMachineNode( Opc, DL, VTList, AddLoArgs);
691 = CurDAG->getMachineNode(CarryOpc, DL, MVT::i32,
728 static SDValue wrapAddr64Rsrc(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
729 return SDValue(DAG->getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::v4i32,
736 SDLoc DL(Addr)
[all...] |
| AMDILCFGStructurizer.cpp | 229 DebugLoc DL = DebugLoc());
231 DebugLoc DL = DebugLoc());
234 DebugLoc DL);
237 DebugLoc DL);
469 int NewOpcode, DebugLoc DL) {
471 ->CreateMachineInstr(TII->get(NewOpcode), DL);
478 int NewOpcode, DebugLoc DL) {
480 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL);
502 MachineBasicBlock::iterator I, int NewOpcode, DebugLoc DL) {
506 MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(NewOpcode), DL);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 704 DebugLoc DL = (InsertPos != PH->end()) ? InsertPos->getDebugLoc()
786 BuildMI(*PH, InsertPos, DL, SubD, SubR);
812 BuildMI(*PH, InsertPos, DL, AddD, AddR)
833 BuildMI(*PH, InsertPos, DL, LsrD, LsrR)
[all...] |
| HexagonInstrInfo.cpp | 125 DebugLoc DL) const{
157 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
160 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
162 BuildMI(&MBB, DL,
168 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
169 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
417 MachineBasicBlock::iterator I, DebugLoc DL,
421 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
425 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
430 BuildMI(MBB, I, DL, get(Hexagon::OR_pp)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 164 DebugLoc DL, unsigned DestReg,
177 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
182 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
366 DebugLoc DL) const {
379 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
387 BuildMI(&MBB, DL, get(SystemZ::BRC))
393 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
554 MachineBasicBlock::iterator MBBI, DebugLoc DL,
559 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
561 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 47 DebugLoc DL, SelectionDAG &DAG,
54 DebugLoc DL, SelectionDAG &DAG) const;
|
| AMDGPUInstrInfo.h | 74 MachineBasicBlock::iterator MI, DebugLoc DL,
142 DebugLoc DL) const;
|
| /external/llvm/lib/IR/ |
| DataLayout.cpp | 45 StructLayout::StructLayout(StructType *ST, const DataLayout &DL) {
54 unsigned TyAlign = ST->isPacked() ? 1 : DL.getABITypeAlignment(Ty);
64 StructSize += DL.getTypeAllocSize(Ty); // Consume space for this data item
798 DataLayoutPass::DataLayoutPass() : ImmutablePass(ID), DL("") {
805 DataLayoutPass::DataLayoutPass(const DataLayout &DL)
806 : ImmutablePass(ID), DL(DL) {
810 DataLayoutPass::DataLayoutPass(const Module *M) : ImmutablePass(ID), DL(M) {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCSubtarget.h | 113 const DataLayout DL;
149 const DataLayout *getDataLayout() const { return &DL; }
|
| /external/llvm/lib/Transforms/Scalar/ |
| LoopInstSimplify.cpp | 77 const DataLayout *DL = DLP ? &DLP->getDataLayout() : nullptr;
119 Value *V = SimplifyInstruction(I, DL, TLI, DT);
|
| /external/llvm/lib/Transforms/Utils/ |
| CloneFunction.cpp | 262 const DataLayout *DL;
269 const DataLayout *DL)
272 NameSuffix(nameSuffix), CodeInfo(codeInfo), DL(DL) {
329 if (Value *V = SimplifyInstruction(NewInst, DL)) {
425 const DataLayout *DL,
436 NameSuffix, CodeInfo, DL);
566 recursivelySimplifyInstruction(PN, DL);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 47 DebugLoc DL, SelectionDAG &DAG,
54 DebugLoc DL, SelectionDAG &DAG) const;
|
| AMDGPUInstrInfo.h | 74 MachineBasicBlock::iterator MI, DebugLoc DL,
142 DebugLoc DL) const;
|
| /external/llvm/include/llvm/IR/ |
| Operator.h | 448 bool accumulateConstantOffset(const DataLayout &DL, APInt &Offset) const {
450 DL.getPointerSizeInBits(getPointerAddressSpace()) &&
464 const StructLayout *SL = DL.getStructLayout(STy);
473 DL.getTypeAllocSize(GTI.getIndexedType()));
|
| Value.h | 414 Value *stripAndAccumulateInBoundsConstantOffsets(const DataLayout &DL,
416 const Value *stripAndAccumulateInBoundsConstantOffsets(const DataLayout &DL,
419 ->stripAndAccumulateInBoundsConstantOffsets(DL, Offset);
433 bool isDereferenceablePointer(const DataLayout *DL = nullptr) const;
|
| /external/llvm/lib/Analysis/ |
| IVUsers.cpp | 127 if (!isa<PHINode>(I) && !isSafeToSpeculativelyExecute(I, DL))
134 if (Width > 64 || (DL && !DL->isLegalInteger(Width)))
257 DL = DLP ? &DLP->getDataLayout() : nullptr;
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| WinCodeViewLineTables.h | 104 void maybeRecordLocation(DebugLoc DL, const MachineFunction *MF);
|
| /external/llvm/lib/Transforms/Vectorize/ |
| LoopVectorize.cpp | 252 DominatorTree *DT, const DataLayout *DL,
255 : OrigLoop(OrigLoop), SE(SE), LI(LI), DT(DT), DL(DL), TLI(TLI),
413 const DataLayout *DL;
462 DominatorTree *DT, const DataLayout *DL,
464 InnerLoopVectorizer(OrigLoop, SE, LI, DT, DL, TLI, 1, UnrollFactor) { }
540 LoopVectorizationLegality(Loop *L, ScalarEvolution *SE, const DataLayout *DL,
543 : NumLoads(0), NumStores(0), NumPredStores(0), TheLoop(L), SE(SE), DL(DL),
778 DebugLoc DL = TheLoop->getStartLoc()
[all...] |
| /external/clang/lib/Frontend/ |
| VerifyDiagnosticConsumer.cpp | 332 DirectiveList *DL = nullptr;
334 DL = ED ? &ED->Errors : nullptr;
336 DL = ED ? &ED->Warnings : nullptr;
338 DL = ED ? &ED->Remarks : nullptr;
340 DL = ED ? &ED->Notes : nullptr;
361 if (!DL)
511 DL->push_back(D.release());
648 DirectiveList &DL, const char *Kind) {
649 if (DL.empty())
654 for (DirectiveList::iterator I = DL.begin(), E = DL.end(); I != E; ++I)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 58 const DataLayout &DL;
155 DebugLoc DL;
342 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXLowerAggrCopies.cpp | 107 const DataLayout *DL = &getAnalysis<DataLayoutPass>().getDataLayout();
123 if (DL->getTypeStoreSize(load->getType()) < MaxAggrCopySize)
169 unsigned numLoads = DL->getTypeStoreSize(load->getType());
|
