| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 375 const SmallVectorImpl<unsigned> &Ops) const {
376 return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
381 const SmallVectorImpl<unsigned> &Ops,
401 for (SmallVectorImpl<unsigned>::const_iterator I = Ops.begin(), E = Ops.end();
417 if (std::find(Ops.begin(), Ops.end(), i) != Ops.end()) {
446 const SmallVectorImpl<unsigned> &Ops,
[all...] |
| InlineSpiller.cpp | 886 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
888 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | 369 ArrayRef<SDValue> Ops) {
370 for (auto& Op : Ops) {
379 ArrayRef<SDUse> Ops) {
380 for (auto& Op : Ops) {
560 AddNodeIDOperands(ID, N->ops());
799 SDValue Ops[] = { Op };
801 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
817 SDValue Ops[] = { Op1, Op2 };
819 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
830 SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, ArrayRef<SDValue> Ops,
[all...] |
| LegalizeVectorTypes.cpp | 470 SmallVector<SDValue, 8> Ops(N->getNumOperands());
472 Ops[i] = GetScalarizedVector(N->getOperand(i));
473 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
[all...] |
| LegalizeTypesGeneric.cpp | 316 SmallVectorImpl<SDValue> &Ops,
327 IntegerToVector(Parts[0], NumElements, Ops, EltVT);
328 IntegerToVector(Parts[1], NumElements, Ops, EltVT);
330 Ops.push_back(DAG.getNode(ISD::BITCAST, DL, EltVT, Op));
358 SmallVector<SDValue, 8> Ops;
359 IntegerToVector(N->getOperand(0), NumElts, Ops, NVT.getVectorElementType());
362 makeArrayRef(Ops.data(), NumElts));
452 SmallVector<SDValue, 16> Ops(NumElts);
453 Ops[0] = N->getOperand(0);
454 SDValue UndefVal = DAG.getUNDEF(Ops[0].getValueType())
[all...] |
| /frameworks/base/services/core/java/com/android/server/ |
| AppOpsService.java | 96 final SparseArray<HashMap<String, Ops>> mUidOps
97 = new SparseArray<HashMap<String, Ops>>();
101 public final static class Ops extends SparseArray<Op> {
106 public Ops(String _packageName, int _uid, boolean _isPrivileged) {
217 HashMap<String, Ops> pkgs = mUidOps.valueAt(i);
218 Iterator<Ops> it = pkgs.values().iterator();
220 Ops ops = it.next(); local
223 curUid = mContext.getPackageManager().getPackageUid(ops.packageName,
224 UserHandle.getUserId(ops.uid))
354 Ops ops = getOpsLocked(uid, packageName, false); local
647 Ops ops = getOpsLocked(uid, packageName, true); local
684 Ops ops = getOpsLocked(uid, packageName, true); local
789 Ops ops = pkgOps.get(packageName); local
849 Ops ops = getOpsLocked(uid, packageName, edit); local
877 Ops ops = getOpsLocked(uid, packageName, true); local
1032 Ops ops = pkgOps.get(pkgName); local
1079 Ops ops = getOpsLocked(pkg.getUid(), pkg.getPackageName(), false); local
1088 List<AppOpsManager.OpEntry> ops = pkg.getOps(); local
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMUnwindOpAsm.cpp | 192 size_t TotalSize = Ops.size() + 1;
199 PersonalityIndex = (Ops.size() <= 3) ? ARM::EHABI::AEABI_UNWIND_CPP_PR0
203 assert(Ops.size() <= 3 && "too many opcodes for __aeabi_unwind_cpp_pr0");
208 size_t TotalSize = Ops.size() + 2;
219 OpStreamer.EmitByte(Ops[j]);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 176 // We only support LOAD/STORE and vector manipulation ops for vectors
680 SDValue Ops [] = {
690 Op->getVTList(), Ops, VT, MMO);
715 SDValue Ops [] = {
738 Op->getVTList(), Ops, VT, MMO);
796 SmallVector<SDValue, 4> Ops;
797 Ops.push_back(BRCOND.getOperand(0));
799 Ops.push_back(Intr->getOperand(i));
800 Ops.push_back(Target);
805 DAG.getVTList(Res), Ops).getNode()
[all...] |
| AMDGPUInstrInfo.h | 98 const SmallVectorImpl<unsigned> &Ops,
102 const SmallVectorImpl<unsigned> &Ops,
114 const SmallVectorImpl<unsigned> &Ops) const override;
|
| AMDGPUInstrInfo.cpp | 175 const SmallVectorImpl<unsigned> &Ops,
183 const SmallVectorImpl<unsigned> &Ops,
190 const SmallVectorImpl<unsigned> &Ops) const {
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 451 SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
472 return CurDAG->getMachineNode(MLAOpc, SDLoc(N), N->getValueType(0), Ops);
486 SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal };
515 return CurDAG->getMachineNode(SMULLOpc, SDLoc(N), N->getValueType(0), Ops);
861 SmallVector<SDValue, 4> Ops;
864 Ops.push_back(
869 Ops.push_back(Regs[i]);
870 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], MVT::i32));
874 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 143 const SmallVectorImpl<unsigned> &Ops,
151 const SmallVectorImpl<unsigned> &Ops,
158 const SmallVectorImpl<unsigned> &Ops) const
|
| AMDGPUInstrInfo.h | 92 const SmallVectorImpl<unsigned> &Ops,
96 const SmallVectorImpl<unsigned> &Ops,
100 const SmallVectorImpl<unsigned> &Ops) const;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 143 const SmallVectorImpl<unsigned> &Ops,
151 const SmallVectorImpl<unsigned> &Ops,
158 const SmallVectorImpl<unsigned> &Ops) const
|
| AMDGPUInstrInfo.h | 92 const SmallVectorImpl<unsigned> &Ops,
96 const SmallVectorImpl<unsigned> &Ops,
100 const SmallVectorImpl<unsigned> &Ops) const;
|
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 141 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
142 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
155 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
156 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
244 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
245 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 482 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
484 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
762 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
763 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
774 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
775 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
781 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
782 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
811 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
812 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| ConstantFolding.h | 57 ArrayRef<Constant *> Ops,
|
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.h | 45 getOpndList(SmallVectorImpl<SDValue> &Ops,
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZSelectionDAGInfo.cpp | 225 SmallVector<SDValue, 5> Ops;
226 Ops.push_back(End);
227 Ops.push_back(DAG.getConstant(0, PtrVT));
228 Ops.push_back(DAG.getConstant(SystemZ::CCMASK_SRST, MVT::i32));
229 Ops.push_back(DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, MVT::i32));
230 Ops.push_back(Glue);
232 End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
|
| /external/llvm/lib/Analysis/ |
| ScalarEvolutionExpander.cpp | 205 /// unnecessary; in its place, just signed-divide Ops[i] by the scale and
305 static void SimplifyAddOperands(SmallVectorImpl<const SCEV *> &Ops,
309 for (unsigned i = Ops.size(); i > 0 && isa<SCEVAddRecExpr>(Ops[i-1]); --i)
311 // Group Ops into non-addrecs and addrecs.
312 SmallVector<const SCEV *, 8> NoAddRecs(Ops.begin(), Ops.end() - NumAddRecs);
313 SmallVector<const SCEV *, 8> AddRecs(Ops.end() - NumAddRecs, Ops.end());
320 Ops.clear()
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGISel.h | 200 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
253 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
|
| /external/llvm/lib/IR/ |
| Constants.cpp | [all...] |
| /external/llvm/lib/DebugInfo/ |
| DWARFDebugFrame.cpp | 69 Operands Ops;
82 Instructions.back().Ops.push_back(Operand1);
87 Instructions.back().Ops.push_back(Operand1);
88 Instructions.back().Ops.push_back(Operand2);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
