| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | 200 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
248 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
251 if (RelaxedOp == Inst.getOpcode()) {
261 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86AsmBackend.cpp | 242 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
249 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
282 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
284 if (RelaxedOp == Inst.getOpcode()) {
|
| X86MCCodeEmitter.cpp | 411 if (MI.getOpcode() == X86::MOV64rm)
[all...] |
| /external/mockito/cglib-and-asm/src/org/mockito/cglib/core/ |
| CodeEmitter.java | 244 public void math(int op, Type type) { mv.visitInsn(type.getOpcode(op)); }
246 public void array_load(Type type) { mv.visitInsn(type.getOpcode(Constants.IALOAD)); }
247 public void array_store(Type type) { mv.visitInsn(type.getOpcode(Constants.IASTORE)); }
399 mv.visitVarInsn(t.getOpcode(Constants.ILOAD), pos);
404 mv.visitVarInsn(t.getOpcode(Constants.ISTORE), pos);
420 mv.visitInsn(state.sig.getReturnType().getOpcode(Constants.IRETURN));
|
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | 510 CastInst::Create(CI->getOpcode(), CI->getOperand(0), CI->getType(), "",
603 CmpInst::Create(CI->getOpcode(),
628 if (User->getOpcode() != Instruction::And ||
661 int ISDOpcode = TLI.InstructionOpcodeToISD(TruncUser->getOpcode());
686 if (ShiftI->getOpcode() == Instruction::AShr)
697 InsertedTrunc = CastInst::Create(TruncI->getOpcode(), InsertedShift,
781 if (ShiftI->getOpcode() == Instruction::AShr)
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 618 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | 46 if (I->getOpcode() == Instruction::Shl) {
53 if (I->getOpcode() == Instruction::Mul) {
60 if (I->getOpcode() == Instruction::Add) {
176 unsigned Opc = I->getOpcode();
248 Instruction::CastOps firstOp = Instruction::CastOps(CI->getOpcode());
301 isEliminableCastPair(CSrc, CI.getOpcode(), CI.getType(), DL)) {
358 unsigned Opc = I->getOpcode();
671 unsigned Opc = I->getOpcode(), Tmp;
[all...] |
| InstCombineSimplifyDemanded.cpp | 159 if (I->getOpcode() == Instruction::And) {
178 } else if (I->getOpcode() == Instruction::Or) {
204 } else if (I->getOpcode() == Instruction::Xor) {
231 switch (I->getOpcode()) {
354 if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() &&
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 186 switch (Op.getOpcode()) {
740 unsigned Opc = Op.getOpcode();
825 if (LHS.getOpcode() == ISD::Constant)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDILCFGStructurizer.cpp | 443 if (I->getOpcode() == AMDGPU::PRED_X) {
596 switch (MI->getOpcode()) {
607 switch (MI->getOpcode()) {
647 else if (!TII->isMov(MI->getOpcode()))
658 if (instr->getOpcode() == AMDGPU::RETURN)
668 if (MI->getOpcode() == AMDGPU::CONTINUE)
725 if (Pre->getOpcode() == AMDGPU::CONTINUE
726 && It->getOpcode() == AMDGPU::ENDLOOP)
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| IndVarSimplify.cpp | 261 if (Incr == nullptr || Incr->getOpcode() != Instruction::FAdd) return;
570 unsigned Opc = UseInstr->getOpcode();
583 unsigned PhiOpc = cast<Instruction>(*PB)->getOpcode();
665 bool IsSigned = Cast->getOpcode() == Instruction::SExt;
666 if (!IsSigned && Cast->getOpcode() != Instruction::ZExt)
795 unsigned Opcode = DU.NarrowUse->getOpcode();
822 BinaryOperator *WideBO = BinaryOperator::Create(NarrowBO->getOpcode(),
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILPeepholeOptimizer.cpp | 402 if (base->getOpcode() == Instruction::Shl) {
404 } else if (base->getOpcode() == Instruction::And) {
427 if (src->getOpcode() == Instruction::Shl && !shift) {
430 } else if (src->getOpcode() == Instruction::And && !mask) {
451 if (inst->getOpcode() != Instruction::Or) {
691 if (inst->getOpcode() != Instruction::And) {
739 if (ShiftInst->getOpcode() == Instruction::Shl) {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsConstantIslandPass.cpp | 81 switch (MI->getOpcode()) {
637 assert(CPEMI && CPEMI->getOpcode() == Mips::CONSTPOOL_ENTRY);
683 int Opc = I->getOpcode();
[all...] |
| MipsSEISelLowering.cpp | 358 switch(Op.getOpcode()) {
393 if (ADDCNode->getOpcode() != ISD::ADDC)
399 unsigned MultOpc = MultHi.getOpcode();
465 if (SUBCNode->getOpcode() != ISD::SUBC)
471 unsigned MultOpc = MultHi.getOpcode();
552 unsigned Op0Opcode = Op0->getOpcode();
620 if (N->getOpcode() == ISD::BITCAST)
642 if (N->getOpcode() != ISD::XOR)
674 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILPeepholeOptimizer.cpp | 402 if (base->getOpcode() == Instruction::Shl) {
404 } else if (base->getOpcode() == Instruction::And) {
427 if (src->getOpcode() == Instruction::Shl && !shift) {
430 } else if (src->getOpcode() == Instruction::And && !mask) {
451 if (inst->getOpcode() != Instruction::Or) {
691 if (inst->getOpcode() != Instruction::And) {
739 if (ShiftInst->getOpcode() == Instruction::Shl) {
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_tgsi.cpp | 156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
187 return translateOpcode(getOpcode()); }
363 switch (getOpcode()) {
404 switch (getOpcode()) {
419 switch (getOpcode()) {
945 return insn.getOpcode() == TGSI_OPCODE_MOV &&
[all...] |
| /external/llvm/lib/TableGen/ |
| Record.cpp | 239 if (BO->getOpcode() == UnOpInit::CAST) {
251 if (BO->getOpcode() == BinOpInit::STRCONCAT) {
312 if (BO->getOpcode() == UnOpInit::CAST) {
323 if (BO->getOpcode() == BinOpInit::CONCAT) {
752 switch (getOpcode()) {
859 return (UnOpInit::get(getOpcode(), lhs, getType()))->Fold(&R, nullptr);
892 switch (getOpcode()) {
963 switch (getOpcode()) {
983 return (BinOpInit::get(getOpcode(), lhs, rhs, getType()))->Fold(&R,nullptr);
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_tgsi.cpp | 156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
187 return translateOpcode(getOpcode()); }
363 switch (getOpcode()) {
404 switch (getOpcode()) {
419 switch (getOpcode()) {
945 return insn.getOpcode() == TGSI_OPCODE_MOV &&
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 108 unsigned Opc = MBBI->getOpcode();
212 unsigned Opc = PI->getOpcode();
243 unsigned Opc = NI->getOpcode();
275 unsigned Opc = PI->getOpcode();
609 (MBBI->getOpcode() == X86::PUSH32r ||
610 MBBI->getOpcode() == X86::PUSH64r)) {
841 unsigned RetOpcode = MBBI->getOpcode();
[all...] |
| /external/llvm/lib/MC/ |
| MCExpr.cpp | 64 switch (UE.getOpcode()) {
84 switch (BE.getOpcode()) {
704 switch (AUE->getOpcode()) {
743 switch (ABE->getOpcode()) {
766 switch (ABE->getOpcode()) {
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/clang/include/clang/AST/ |
| Expr.h | [all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| SsaMethod.java | 690 && insn.getOpcode().getOpcode() == RegOps.MARK_LOCAL) {
842 || lastInsn.getOriginalRopInsn().getOpcode()
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| SymbolManager.cpp | 34 << BinaryOperator::getOpcodeStr(getOpcode()) << ' '
45 << BinaryOperator::getOpcodeStr(getOpcode())
55 << BinaryOperator::getOpcodeStr(getOpcode())
|
