| /external/llvm/test/MC/AArch64/ |
| elf-reloc-ldstunsimm.s | 4 ldrb w0, [sp, #:lo12:some_label]
5 ldrh w0, [sp, #:lo12:some_label]
6 ldr w0, [sp, #:lo12:some_label]
7 ldr x0, [sp, #:lo12:some_label]
8 str q0, [sp, #:lo12:some_label]
|
| arm64-elf-relocs.s | 4 add x0, x2, #:lo12:sym
5 // CHECK: add x0, x2, :lo12:sym
28 add x0, x2, #:lo12:sym+8
29 // CHECK: add x0, x2, :lo12:sym
91 ldrb w2, [x3, :lo12:sym]
92 ldrsb w5, [x7, #:lo12:sym]
93 ldrsb x11, [x13, :lo12:sym]
94 ldr b17, [x19, #:lo12:sym]
95 // CHECK: ldrb w2, [x3, :lo12:sym]
96 // CHECK: ldrsb w5, [x7, :lo12:sym
[all...] |
| elf-reloc-addsubimm.s | 4 add x2, x3, #:lo12:some_label
|
| jump-table.s | 15 add x0, x0, #:lo12:.LJTI0_0
47 // First make sure we get a page/lo12 pair in .text to pick up the jump-table
|
| basic-pic.s | 43 ldr w0, [x0, #:lo12:hiddenvar]
57 add x0, x0, #:lo12:hiddenvar
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-elf-globals.ll | 17 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
18 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
26 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
39 ; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
40 ; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
43 ; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
52 ; CHECK: ldr {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
53 ; CHECK: str {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
56 ; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var32
65 ; CHECK: ldr {{x[0-9]+}}, [x[[HIREG]], :lo12:var64
[all...] |
| global-alignment.ll | 13 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
16 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:var32
31 ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:var64]
41 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
45 ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:var32_align64]
58 ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:alias]
73 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:yet_another_var
82 ; CHECK: add x0, [[HIBITS]], {{#?}}:lo12:test_yet_another_var
|
| bool-loads.ll | 10 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
22 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
37 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
51 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
|
| ldst-unsignedimm.ll | 23 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
29 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
35 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
41 ; CHECK: ldrsb {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
49 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
55 ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
61 ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
77 ; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
83 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
89 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit
[all...] |
| arm64-fp128.ll | 11 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
12 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
24 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
25 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
37 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
38 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
50 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
51 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
128 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
129 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs
[all...] |
| arm64-aapcs.ll | 7 ; CHECK: str w4, [{{x[0-9]+}}, :lo12:var]
26 ; CHECK: str x[[EXTED]], [{{x[0-9]+}}, :lo12:var64]
31 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
36 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
41 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
44 ; CHECK: str [[LONG]], [{{x[0-9]+}}, :lo12:var64]
56 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
61 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
66 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
71 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64
[all...] |
| arm64-elf-constpool.ll | 12 ; CHECK: ldr d0, [{{x[0-9]+}}, :lo12:.LCPI0_0]
|
| breg.ll | 10 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:stored_label]
|
| funcptr_cast.ll | 6 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, :lo12:foo
|
| i1-contents.ll | 11 ; CHECK: str [[BOOL32]], [{{x[0-9]+}}, :lo12:var]
23 ; CHECK: str [[BOOL32]], [{{x[0-9]+}}, :lo12:var]
33 ; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var]
42 ; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var]
|
| func-calls.ll | 27 ; CHECK-DAG: ldrb w0, [{{x[0-9]+}}, {{#?}}:lo12:var8]
28 ; CHECK-DAG: ldrb w1, [{{x[0-9]+}}, {{#?}}:lo12:var8_2]
34 ; CHECK-DAG: ldr s1, [{{x[0-9]+}}, {{#?}}:lo12:varfloat_2]
35 ; CHECK-DAG: ldr s0, [{{x[0-9]+}}, {{#?}}:lo12:varfloat]
54 ; CHECK: str w0, [{{x[0-9]+}}, {{#?}}:lo12:var32]
59 ; CHECK: str d0, [{{x[0-9]+}}, {{#?}}:lo12:vardouble]
66 ; CHECK: str x0, [{{x[0-9]+}}, {{#?}}:lo12:varsmallstruct]
69 ; CHECK: add x8, {{x[0-9]+}}, {{#?}}:lo12:varstruct
131 ; CHECK: ldr [[I128LO:x[0-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:var128]
135 ; CHECK-NONEON: ldr [[I128LO:x[0-9]+]], [{{x[0-9]+}}, :lo12:var128
[all...] |
| arm64-pic-local-symbol.ll | 9 ; CHECK-NEXT: ldr w{{[0-9]+}}, [x{{[0-9]}}, :lo12:a]
17 ; CHECK-NEXT: add x{{[0-9]}}, x{{[0-9]}}, :lo12:.L.str
|
| arm64-variadic-aapcs.ll | 24 ; CHECK: str [[STACK_TOP]], [x[[VA_LIST_HI]], :lo12:var]
28 ; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
62 ; CHECK: str [[STACK_TOP]], [x[[VA_LIST_HI]], :lo12:var]
66 ; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
92 ; CHECK: str [[STACK]], [{{x[0-9]+}}, :lo12:var]
103 ; CHECK: str [[STACK_TOP]], [{{x[0-9]+}}, :lo12:var]
133 ; CHECK: add x[[SRC:[0-9]+]], {{x[0-9]+}}, :lo12:var
136 ; CHECK: add x[[DST:[0-9]+]], {{x[0-9]+}}, :lo12:second_list
|
| fpimm.ll | 16 ; CHECK-DAG: ldr [[HARD:s[0-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:.LCPI0_0
32 ; CHECK-DAG: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI1_0
|
| zero-reg.ll | 10 ; CHECK: str wzr, [{{x[0-9]+}}, {{#?}}:lo12:var32]
12 ; CHECK: str xzr, [{{x[0-9]+}}, {{#?}}:lo12:var64]
|
| func-argpassing.ll | 19 ; CHECK: strb w1, [{{x[0-9]+}}, {{#?}}:lo12:var8]
29 ; CHECK: str [[ADDRES]], [{{x[0-9]+}}, {{#?}}:lo12:varfloat]
44 ; CHECK: str [[REG32]], [{{x[0-9]+}}, {{#?}}:lo12:var32]
49 ; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64]
65 ; CHECK: str [[REG32]], [{{x[0-9]+}}, {{#?}}:lo12:var32]
70 ; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64]
79 ; CHECK: ldr w0, [{{x[0-9]+}}, {{#?}}:lo12:var32]
87 ; CHECK: ldr d0, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI
99 ; CHECK-DAG: ldr x0, [{{x[0-9]+}}, {{#?}}:lo12:varstruct]
101 ; CHECK-DAG: add {{x[1-9][0-9]*}}, {{x[1-9][0-9]*}}, {{#?}}:lo12:varstruc
[all...] |
| fp128-folding.ll | 15 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI
|
| arm64-basic-pic.ll | 33 ; CHECK: ldr w0, [x[[HI]], :lo12:hiddenvar]
43 ; CHECK: add x0, [[HI]], :lo12:hiddenvar
|
| basic-pic.ll | 33 ; CHECK: ldr w0, [x[[HI]], {{#?}}:lo12:hiddenvar]
43 ; CHECK: add x0, [[HI]], {{#?}}:lo12:hiddenvar
|
| atomic-ops.ll | 20 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
40 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
60 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
80 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
100 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
120 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
140 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
160 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
180 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
200 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var1
[all...] |
