1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Interface definition for SIInstrInfo. 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 #ifndef SIINSTRINFO_H 17 #define SIINSTRINFO_H 18 19 #include "AMDGPUInstrInfo.h" 20 #include "SIRegisterInfo.h" 21 22 namespace llvm { 23 24 class SIInstrInfo : public AMDGPUInstrInfo { 25 private: 26 const SIRegisterInfo RI; 27 28 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, 29 MachineRegisterInfo &MRI, 30 MachineOperand &SuperReg, 31 const TargetRegisterClass *SuperRC, 32 unsigned SubIdx, 33 const TargetRegisterClass *SubRC) const; 34 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, 35 MachineRegisterInfo &MRI, 36 MachineOperand &SuperReg, 37 const TargetRegisterClass *SuperRC, 38 unsigned SubIdx, 39 const TargetRegisterClass *SubRC) const; 40 41 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist, 42 MachineBasicBlock::iterator MI, 43 MachineRegisterInfo &MRI, 44 const TargetRegisterClass *RC, 45 const MachineOperand &Op) const; 46 47 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist, 48 MachineInstr *Inst, unsigned Opcode) const; 49 50 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist, 51 MachineInstr *Inst, unsigned Opcode) const; 52 53 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist, 54 MachineInstr *Inst) const; 55 56 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const; 57 58 public: 59 explicit SIInstrInfo(const AMDGPUSubtarget &st); 60 61 const SIRegisterInfo &getRegisterInfo() const override { 62 return RI; 63 } 64 65 void copyPhysReg(MachineBasicBlock &MBB, 66 MachineBasicBlock::iterator MI, DebugLoc DL, 67 unsigned DestReg, unsigned SrcReg, 68 bool KillSrc) const override; 69 70 void storeRegToStackSlot(MachineBasicBlock &MBB, 71 MachineBasicBlock::iterator MI, 72 unsigned SrcReg, bool isKill, int FrameIndex, 73 const TargetRegisterClass *RC, 74 const TargetRegisterInfo *TRI) const override; 75 76 void loadRegFromStackSlot(MachineBasicBlock &MBB, 77 MachineBasicBlock::iterator MI, 78 unsigned DestReg, int FrameIndex, 79 const TargetRegisterClass *RC, 80 const TargetRegisterInfo *TRI) const override; 81 82 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 83 84 unsigned commuteOpcode(unsigned Opcode) const; 85 86 MachineInstr *commuteInstruction(MachineInstr *MI, 87 bool NewMI=false) const override; 88 89 bool isTriviallyReMaterializable(const MachineInstr *MI, 90 AliasAnalysis *AA = nullptr) const; 91 92 unsigned getIEQOpcode() const override { 93 llvm_unreachable("Unimplemented"); 94 } 95 96 MachineInstr *buildMovInstr(MachineBasicBlock *MBB, 97 MachineBasicBlock::iterator I, 98 unsigned DstReg, unsigned SrcReg) const override; 99 bool isMov(unsigned Opcode) const override; 100 101 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; 102 bool isDS(uint16_t Opcode) const; 103 int isMIMG(uint16_t Opcode) const; 104 int isSMRD(uint16_t Opcode) const; 105 bool isVOP1(uint16_t Opcode) const; 106 bool isVOP2(uint16_t Opcode) const; 107 bool isVOP3(uint16_t Opcode) const; 108 bool isVOPC(uint16_t Opcode) const; 109 bool isInlineConstant(const APInt &Imm) const; 110 bool isInlineConstant(const MachineOperand &MO) const; 111 bool isLiteralConstant(const MachineOperand &MO) const; 112 113 bool verifyInstruction(const MachineInstr *MI, 114 StringRef &ErrInfo) const override; 115 116 bool isSALUInstr(const MachineInstr &MI) const; 117 static unsigned getVALUOp(const MachineInstr &MI); 118 119 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const; 120 121 /// \brief Return the correct register class for \p OpNo. For target-specific 122 /// instructions, this will return the register class that has been defined 123 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return 124 /// the register class of its machine operand. 125 /// to infer the correct register class base on the other operands. 126 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI, 127 unsigned OpNo) const;\ 128 129 /// \returns true if it is legal for the operand at index \p OpNo 130 /// to read a VGPR. 131 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const; 132 133 /// \brief Legalize the \p OpIndex operand of this instruction by inserting 134 /// a MOV. For example: 135 /// ADD_I32_e32 VGPR0, 15 136 /// to 137 /// MOV VGPR1, 15 138 /// ADD_I32_e32 VGPR0, VGPR1 139 /// 140 /// If the operand being legalized is a register, then a COPY will be used 141 /// instead of MOV. 142 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const; 143 144 /// \brief Legalize all operands in this instruction. This function may 145 /// create new instruction and insert them before \p MI. 146 void legalizeOperands(MachineInstr *MI) const; 147 148 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const; 149 150 /// \brief Replace this instruction's opcode with the equivalent VALU 151 /// opcode. This function will also move the users of \p MI to the 152 /// VALU if necessary. 153 void moveToVALU(MachineInstr &MI) const; 154 155 unsigned calculateIndirectAddress(unsigned RegIndex, 156 unsigned Channel) const override; 157 158 const TargetRegisterClass *getIndirectAddrRegClass() const override; 159 160 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 161 MachineBasicBlock::iterator I, 162 unsigned ValueReg, 163 unsigned Address, 164 unsigned OffsetReg) const override; 165 166 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 167 MachineBasicBlock::iterator I, 168 unsigned ValueReg, 169 unsigned Address, 170 unsigned OffsetReg) const override; 171 void reserveIndirectRegisters(BitVector &Reserved, 172 const MachineFunction &MF) const; 173 174 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I, 175 unsigned SavReg, unsigned IndexReg) const; 176 177 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const; 178 }; 179 180 namespace AMDGPU { 181 182 int getVOPe64(uint16_t Opcode); 183 int getCommuteRev(uint16_t Opcode); 184 int getCommuteOrig(uint16_t Opcode); 185 int getMCOpcode(uint16_t Opcode, unsigned Gen); 186 187 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL; 188 189 190 } // End namespace AMDGPU 191 192 } // End namespace llvm 193 194 namespace SIInstrFlags { 195 enum Flags { 196 // First 4 bits are the instruction encoding 197 VM_CNT = 1 << 0, 198 EXP_CNT = 1 << 1, 199 LGKM_CNT = 1 << 2 200 }; 201 } 202 203 #endif //SIINSTRINFO_H 204
