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      1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the X86 specific subclass of TargetMachine.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "X86TargetMachine.h"
     15 #include "X86.h"
     16 #include "llvm/CodeGen/Passes.h"
     17 #include "llvm/PassManager.h"
     18 #include "llvm/Support/CommandLine.h"
     19 #include "llvm/Support/FormattedStream.h"
     20 #include "llvm/Support/TargetRegistry.h"
     21 #include "llvm/Target/TargetOptions.h"
     22 using namespace llvm;
     23 
     24 extern "C" void LLVMInitializeX86Target() {
     25   // Register the target.
     26   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
     27   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
     28 }
     29 
     30 void X86TargetMachine::anchor() { }
     31 
     32 /// X86TargetMachine ctor - Create an X86 target.
     33 ///
     34 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
     35                                    StringRef FS, const TargetOptions &Options,
     36                                    Reloc::Model RM, CodeModel::Model CM,
     37                                    CodeGenOpt::Level OL)
     38     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
     39       Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
     40   // Determine the PICStyle based on the target selected.
     41   if (getRelocationModel() == Reloc::Static) {
     42     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
     43     Subtarget.setPICStyle(PICStyles::None);
     44   } else if (Subtarget.is64Bit()) {
     45     // PIC in 64 bit mode is always rip-rel.
     46     Subtarget.setPICStyle(PICStyles::RIPRel);
     47   } else if (Subtarget.isTargetCOFF()) {
     48     Subtarget.setPICStyle(PICStyles::None);
     49   } else if (Subtarget.isTargetDarwin()) {
     50     if (getRelocationModel() == Reloc::PIC_)
     51       Subtarget.setPICStyle(PICStyles::StubPIC);
     52     else {
     53       assert(getRelocationModel() == Reloc::DynamicNoPIC);
     54       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
     55     }
     56   } else if (Subtarget.isTargetELF()) {
     57     Subtarget.setPICStyle(PICStyles::GOT);
     58   }
     59 
     60   // default to hard float ABI
     61   if (Options.FloatABIType == FloatABI::Default)
     62     this->Options.FloatABIType = FloatABI::Hard;
     63 
     64   // Windows stack unwinder gets confused when execution flow "falls through"
     65   // after a call to 'noreturn' function.
     66   // To prevent that, we emit a trap for 'unreachable' IR instructions.
     67   // (which on X86, happens to be the 'ud2' instruction)
     68   if (Subtarget.isTargetWin64())
     69     this->Options.TrapUnreachable = true;
     70 
     71   initAsmInfo();
     72 }
     73 
     74 //===----------------------------------------------------------------------===//
     75 // Command line options for x86
     76 //===----------------------------------------------------------------------===//
     77 static cl::opt<bool>
     78 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
     79   cl::desc("Minimize AVX to SSE transition penalty"),
     80   cl::init(true));
     81 
     82 //===----------------------------------------------------------------------===//
     83 // X86 Analysis Pass Setup
     84 //===----------------------------------------------------------------------===//
     85 
     86 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
     87   // Add first the target-independent BasicTTI pass, then our X86 pass. This
     88   // allows the X86 pass to delegate to the target independent layer when
     89   // appropriate.
     90   PM.add(createBasicTargetTransformInfoPass(this));
     91   PM.add(createX86TargetTransformInfoPass(this));
     92 }
     93 
     94 
     95 //===----------------------------------------------------------------------===//
     96 // Pass Pipeline Configuration
     97 //===----------------------------------------------------------------------===//
     98 
     99 namespace {
    100 /// X86 Code Generator Pass Configuration Options.
    101 class X86PassConfig : public TargetPassConfig {
    102 public:
    103   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
    104     : TargetPassConfig(TM, PM) {}
    105 
    106   X86TargetMachine &getX86TargetMachine() const {
    107     return getTM<X86TargetMachine>();
    108   }
    109 
    110   const X86Subtarget &getX86Subtarget() const {
    111     return *getX86TargetMachine().getSubtargetImpl();
    112   }
    113 
    114   void addIRPasses() override;
    115   bool addInstSelector() override;
    116   bool addILPOpts() override;
    117   bool addPreRegAlloc() override;
    118   bool addPostRegAlloc() override;
    119   bool addPreEmitPass() override;
    120 };
    121 } // namespace
    122 
    123 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
    124   return new X86PassConfig(this, PM);
    125 }
    126 
    127 void X86PassConfig::addIRPasses() {
    128   addPass(createX86AtomicExpandPass(&getX86TargetMachine()));
    129 
    130   TargetPassConfig::addIRPasses();
    131 }
    132 
    133 bool X86PassConfig::addInstSelector() {
    134   // Install an instruction selector.
    135   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
    136 
    137   // For ELF, cleanup any local-dynamic TLS accesses.
    138   if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
    139     addPass(createCleanupLocalDynamicTLSPass());
    140 
    141   addPass(createX86GlobalBaseRegPass());
    142 
    143   return false;
    144 }
    145 
    146 bool X86PassConfig::addILPOpts() {
    147   addPass(&EarlyIfConverterID);
    148   return true;
    149 }
    150 
    151 bool X86PassConfig::addPreRegAlloc() {
    152   return false;  // -print-machineinstr shouldn't print after this.
    153 }
    154 
    155 bool X86PassConfig::addPostRegAlloc() {
    156   addPass(createX86FloatingPointStackifierPass());
    157   return true;  // -print-machineinstr should print after this.
    158 }
    159 
    160 bool X86PassConfig::addPreEmitPass() {
    161   bool ShouldPrint = false;
    162   if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
    163     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
    164     ShouldPrint = true;
    165   }
    166 
    167   if (UseVZeroUpper) {
    168     addPass(createX86IssueVZeroUpperPass());
    169     ShouldPrint = true;
    170   }
    171 
    172   if (getOptLevel() != CodeGenOpt::None) {
    173     addPass(createX86PadShortFunctions());
    174     addPass(createX86FixupLEAs());
    175     ShouldPrint = true;
    176   }
    177 
    178   return ShouldPrint;
    179 }
    180 
    181 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
    182                                       JITCodeEmitter &JCE) {
    183   PM.add(createX86JITCodeEmitterPass(*this, JCE));
    184 
    185   return false;
    186 }
    187