1 /* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #include "dex/compiler_ir.h" 18 #include "dex/frontend.h" 19 #include "dex/quick/dex_file_method_inliner.h" 20 #include "dex/quick/dex_file_to_method_inliner_map.h" 21 #include "dex_file-inl.h" 22 #include "entrypoints/quick/quick_entrypoints.h" 23 #include "invoke_type.h" 24 #include "mirror/array.h" 25 #include "mirror/class-inl.h" 26 #include "mirror/dex_cache.h" 27 #include "mirror/object_array-inl.h" 28 #include "mirror/reference-inl.h" 29 #include "mirror/string.h" 30 #include "mir_to_lir-inl.h" 31 #include "scoped_thread_state_change.h" 32 #include "x86/codegen_x86.h" 33 34 namespace art { 35 36 // Shortcuts to repeatedly used long types. 37 typedef mirror::ObjectArray<mirror::Object> ObjArray; 38 39 /* 40 * This source files contains "gen" codegen routines that should 41 * be applicable to most targets. Only mid-level support utilities 42 * and "op" calls may be used here. 43 */ 44 45 void Mir2Lir::AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume) { 46 class IntrinsicSlowPathPath : public Mir2Lir::LIRSlowPath { 47 public: 48 IntrinsicSlowPathPath(Mir2Lir* m2l, CallInfo* info, LIR* branch, LIR* resume = nullptr) 49 : LIRSlowPath(m2l, info->offset, branch, resume), info_(info) { 50 } 51 52 void Compile() { 53 m2l_->ResetRegPool(); 54 m2l_->ResetDefTracking(); 55 GenerateTargetLabel(kPseudoIntrinsicRetry); 56 // NOTE: GenInvokeNoInline() handles MarkSafepointPC. 57 m2l_->GenInvokeNoInline(info_); 58 if (cont_ != nullptr) { 59 m2l_->OpUnconditionalBranch(cont_); 60 } 61 } 62 63 private: 64 CallInfo* const info_; 65 }; 66 67 AddSlowPath(new (arena_) IntrinsicSlowPathPath(this, info, branch, resume)); 68 } 69 70 /* 71 * To save scheduling time, helper calls are broken into two parts: generation of 72 * the helper target address, and the actual call to the helper. Because x86 73 * has a memory call operation, part 1 is a NOP for x86. For other targets, 74 * load arguments between the two parts. 75 */ 76 // template <size_t pointer_size> 77 RegStorage Mir2Lir::CallHelperSetup(QuickEntrypointEnum trampoline) { 78 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 79 return RegStorage::InvalidReg(); 80 } else { 81 return LoadHelper(trampoline); 82 } 83 } 84 85 LIR* Mir2Lir::CallHelper(RegStorage r_tgt, QuickEntrypointEnum trampoline, bool safepoint_pc, 86 bool use_link) { 87 LIR* call_inst = InvokeTrampoline(use_link ? kOpBlx : kOpBx, r_tgt, trampoline); 88 89 if (r_tgt.Valid()) { 90 FreeTemp(r_tgt); 91 } 92 93 if (safepoint_pc) { 94 MarkSafepointPC(call_inst); 95 } 96 return call_inst; 97 } 98 99 void Mir2Lir::CallRuntimeHelper(QuickEntrypointEnum trampoline, bool safepoint_pc) { 100 RegStorage r_tgt = CallHelperSetup(trampoline); 101 ClobberCallerSave(); 102 CallHelper(r_tgt, trampoline, safepoint_pc); 103 } 104 105 void Mir2Lir::CallRuntimeHelperImm(QuickEntrypointEnum trampoline, int arg0, bool safepoint_pc) { 106 RegStorage r_tgt = CallHelperSetup(trampoline); 107 LoadConstant(TargetReg(kArg0, kNotWide), arg0); 108 ClobberCallerSave(); 109 CallHelper(r_tgt, trampoline, safepoint_pc); 110 } 111 112 void Mir2Lir::CallRuntimeHelperReg(QuickEntrypointEnum trampoline, RegStorage arg0, 113 bool safepoint_pc) { 114 RegStorage r_tgt = CallHelperSetup(trampoline); 115 OpRegCopy(TargetReg(kArg0, arg0.GetWideKind()), arg0); 116 ClobberCallerSave(); 117 CallHelper(r_tgt, trampoline, safepoint_pc); 118 } 119 120 void Mir2Lir::CallRuntimeHelperRegLocation(QuickEntrypointEnum trampoline, RegLocation arg0, 121 bool safepoint_pc) { 122 RegStorage r_tgt = CallHelperSetup(trampoline); 123 if (arg0.wide == 0) { 124 LoadValueDirectFixed(arg0, TargetReg(arg0.fp ? kFArg0 : kArg0, arg0)); 125 } else { 126 LoadValueDirectWideFixed(arg0, TargetReg(arg0.fp ? kFArg0 : kArg0, kWide)); 127 } 128 ClobberCallerSave(); 129 CallHelper(r_tgt, trampoline, safepoint_pc); 130 } 131 132 void Mir2Lir::CallRuntimeHelperImmImm(QuickEntrypointEnum trampoline, int arg0, int arg1, 133 bool safepoint_pc) { 134 RegStorage r_tgt = CallHelperSetup(trampoline); 135 LoadConstant(TargetReg(kArg0, kNotWide), arg0); 136 LoadConstant(TargetReg(kArg1, kNotWide), arg1); 137 ClobberCallerSave(); 138 CallHelper(r_tgt, trampoline, safepoint_pc); 139 } 140 141 void Mir2Lir::CallRuntimeHelperImmRegLocation(QuickEntrypointEnum trampoline, int arg0, 142 RegLocation arg1, bool safepoint_pc) { 143 RegStorage r_tgt = CallHelperSetup(trampoline); 144 if (arg1.wide == 0) { 145 LoadValueDirectFixed(arg1, TargetReg(kArg1, arg1)); 146 } else { 147 RegStorage r_tmp = TargetReg(cu_->instruction_set == kMips ? kArg2 : kArg1, kWide); 148 LoadValueDirectWideFixed(arg1, r_tmp); 149 } 150 LoadConstant(TargetReg(kArg0, kNotWide), arg0); 151 ClobberCallerSave(); 152 CallHelper(r_tgt, trampoline, safepoint_pc); 153 } 154 155 void Mir2Lir::CallRuntimeHelperRegLocationImm(QuickEntrypointEnum trampoline, RegLocation arg0, 156 int arg1, bool safepoint_pc) { 157 RegStorage r_tgt = CallHelperSetup(trampoline); 158 DCHECK(!arg0.wide); 159 LoadValueDirectFixed(arg0, TargetReg(kArg0, arg0)); 160 LoadConstant(TargetReg(kArg1, kNotWide), arg1); 161 ClobberCallerSave(); 162 CallHelper(r_tgt, trampoline, safepoint_pc); 163 } 164 165 void Mir2Lir::CallRuntimeHelperImmReg(QuickEntrypointEnum trampoline, int arg0, RegStorage arg1, 166 bool safepoint_pc) { 167 RegStorage r_tgt = CallHelperSetup(trampoline); 168 OpRegCopy(TargetReg(kArg1, arg1.GetWideKind()), arg1); 169 LoadConstant(TargetReg(kArg0, kNotWide), arg0); 170 ClobberCallerSave(); 171 CallHelper(r_tgt, trampoline, safepoint_pc); 172 } 173 174 void Mir2Lir::CallRuntimeHelperRegImm(QuickEntrypointEnum trampoline, RegStorage arg0, int arg1, 175 bool safepoint_pc) { 176 RegStorage r_tgt = CallHelperSetup(trampoline); 177 OpRegCopy(TargetReg(kArg0, arg0.GetWideKind()), arg0); 178 LoadConstant(TargetReg(kArg1, kNotWide), arg1); 179 ClobberCallerSave(); 180 CallHelper(r_tgt, trampoline, safepoint_pc); 181 } 182 183 void Mir2Lir::CallRuntimeHelperImmMethod(QuickEntrypointEnum trampoline, int arg0, 184 bool safepoint_pc) { 185 RegStorage r_tgt = CallHelperSetup(trampoline); 186 LoadCurrMethodDirect(TargetReg(kArg1, kRef)); 187 LoadConstant(TargetReg(kArg0, kNotWide), arg0); 188 ClobberCallerSave(); 189 CallHelper(r_tgt, trampoline, safepoint_pc); 190 } 191 192 void Mir2Lir::CallRuntimeHelperRegMethod(QuickEntrypointEnum trampoline, RegStorage arg0, 193 bool safepoint_pc) { 194 RegStorage r_tgt = CallHelperSetup(trampoline); 195 DCHECK(!IsSameReg(TargetReg(kArg1, arg0.GetWideKind()), arg0)); 196 RegStorage r_tmp = TargetReg(kArg0, arg0.GetWideKind()); 197 if (r_tmp.NotExactlyEquals(arg0)) { 198 OpRegCopy(r_tmp, arg0); 199 } 200 LoadCurrMethodDirect(TargetReg(kArg1, kRef)); 201 ClobberCallerSave(); 202 CallHelper(r_tgt, trampoline, safepoint_pc); 203 } 204 205 void Mir2Lir::CallRuntimeHelperRegMethodRegLocation(QuickEntrypointEnum trampoline, RegStorage arg0, 206 RegLocation arg2, bool safepoint_pc) { 207 RegStorage r_tgt = CallHelperSetup(trampoline); 208 DCHECK(!IsSameReg(TargetReg(kArg1, arg0.GetWideKind()), arg0)); 209 RegStorage r_tmp = TargetReg(kArg0, arg0.GetWideKind()); 210 if (r_tmp.NotExactlyEquals(arg0)) { 211 OpRegCopy(r_tmp, arg0); 212 } 213 LoadCurrMethodDirect(TargetReg(kArg1, kRef)); 214 LoadValueDirectFixed(arg2, TargetReg(kArg2, arg2)); 215 ClobberCallerSave(); 216 CallHelper(r_tgt, trampoline, safepoint_pc); 217 } 218 219 void Mir2Lir::CallRuntimeHelperRegLocationRegLocation(QuickEntrypointEnum trampoline, 220 RegLocation arg0, RegLocation arg1, 221 bool safepoint_pc) { 222 RegStorage r_tgt = CallHelperSetup(trampoline); 223 if (cu_->instruction_set == kArm64 || cu_->instruction_set == kX86_64) { 224 RegStorage arg0_reg = TargetReg((arg0.fp) ? kFArg0 : kArg0, arg0); 225 226 RegStorage arg1_reg; 227 if (arg1.fp == arg0.fp) { 228 arg1_reg = TargetReg((arg1.fp) ? kFArg1 : kArg1, arg1); 229 } else { 230 arg1_reg = TargetReg((arg1.fp) ? kFArg0 : kArg0, arg1); 231 } 232 233 if (arg0.wide == 0) { 234 LoadValueDirectFixed(arg0, arg0_reg); 235 } else { 236 LoadValueDirectWideFixed(arg0, arg0_reg); 237 } 238 239 if (arg1.wide == 0) { 240 LoadValueDirectFixed(arg1, arg1_reg); 241 } else { 242 LoadValueDirectWideFixed(arg1, arg1_reg); 243 } 244 } else { 245 DCHECK(!cu_->target64); 246 if (arg0.wide == 0) { 247 LoadValueDirectFixed(arg0, TargetReg(arg0.fp ? kFArg0 : kArg0, kNotWide)); 248 if (arg1.wide == 0) { 249 if (cu_->instruction_set == kMips) { 250 LoadValueDirectFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg1, kNotWide)); 251 } else { 252 LoadValueDirectFixed(arg1, TargetReg(kArg1, kNotWide)); 253 } 254 } else { 255 if (cu_->instruction_set == kMips) { 256 LoadValueDirectWideFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg2, kWide)); 257 } else { 258 LoadValueDirectWideFixed(arg1, TargetReg(kArg1, kWide)); 259 } 260 } 261 } else { 262 LoadValueDirectWideFixed(arg0, TargetReg(arg0.fp ? kFArg0 : kArg0, kWide)); 263 if (arg1.wide == 0) { 264 LoadValueDirectFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg2, kNotWide)); 265 } else { 266 LoadValueDirectWideFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg2, kWide)); 267 } 268 } 269 } 270 ClobberCallerSave(); 271 CallHelper(r_tgt, trampoline, safepoint_pc); 272 } 273 274 void Mir2Lir::CopyToArgumentRegs(RegStorage arg0, RegStorage arg1) { 275 WideKind arg0_kind = arg0.GetWideKind(); 276 WideKind arg1_kind = arg1.GetWideKind(); 277 if (IsSameReg(arg1, TargetReg(kArg0, arg1_kind))) { 278 if (IsSameReg(arg0, TargetReg(kArg1, arg0_kind))) { 279 // Swap kArg0 and kArg1 with kArg2 as temp. 280 OpRegCopy(TargetReg(kArg2, arg1_kind), arg1); 281 OpRegCopy(TargetReg(kArg0, arg0_kind), arg0); 282 OpRegCopy(TargetReg(kArg1, arg1_kind), TargetReg(kArg2, arg1_kind)); 283 } else { 284 OpRegCopy(TargetReg(kArg1, arg1_kind), arg1); 285 OpRegCopy(TargetReg(kArg0, arg0_kind), arg0); 286 } 287 } else { 288 OpRegCopy(TargetReg(kArg0, arg0_kind), arg0); 289 OpRegCopy(TargetReg(kArg1, arg1_kind), arg1); 290 } 291 } 292 293 void Mir2Lir::CallRuntimeHelperRegReg(QuickEntrypointEnum trampoline, RegStorage arg0, 294 RegStorage arg1, bool safepoint_pc) { 295 RegStorage r_tgt = CallHelperSetup(trampoline); 296 CopyToArgumentRegs(arg0, arg1); 297 ClobberCallerSave(); 298 CallHelper(r_tgt, trampoline, safepoint_pc); 299 } 300 301 void Mir2Lir::CallRuntimeHelperRegRegImm(QuickEntrypointEnum trampoline, RegStorage arg0, 302 RegStorage arg1, int arg2, bool safepoint_pc) { 303 RegStorage r_tgt = CallHelperSetup(trampoline); 304 CopyToArgumentRegs(arg0, arg1); 305 LoadConstant(TargetReg(kArg2, kNotWide), arg2); 306 ClobberCallerSave(); 307 CallHelper(r_tgt, trampoline, safepoint_pc); 308 } 309 310 void Mir2Lir::CallRuntimeHelperImmMethodRegLocation(QuickEntrypointEnum trampoline, int arg0, 311 RegLocation arg2, bool safepoint_pc) { 312 RegStorage r_tgt = CallHelperSetup(trampoline); 313 LoadValueDirectFixed(arg2, TargetReg(kArg2, arg2)); 314 LoadCurrMethodDirect(TargetReg(kArg1, kRef)); 315 LoadConstant(TargetReg(kArg0, kNotWide), arg0); 316 ClobberCallerSave(); 317 CallHelper(r_tgt, trampoline, safepoint_pc); 318 } 319 320 void Mir2Lir::CallRuntimeHelperImmMethodImm(QuickEntrypointEnum trampoline, int arg0, int arg2, 321 bool safepoint_pc) { 322 RegStorage r_tgt = CallHelperSetup(trampoline); 323 LoadCurrMethodDirect(TargetReg(kArg1, kRef)); 324 LoadConstant(TargetReg(kArg2, kNotWide), arg2); 325 LoadConstant(TargetReg(kArg0, kNotWide), arg0); 326 ClobberCallerSave(); 327 CallHelper(r_tgt, trampoline, safepoint_pc); 328 } 329 330 void Mir2Lir::CallRuntimeHelperImmRegLocationRegLocation(QuickEntrypointEnum trampoline, int arg0, 331 RegLocation arg1, 332 RegLocation arg2, bool safepoint_pc) { 333 RegStorage r_tgt = CallHelperSetup(trampoline); 334 DCHECK_EQ(static_cast<unsigned int>(arg1.wide), 0U); // The static_cast works around an 335 // instantiation bug in GCC. 336 LoadValueDirectFixed(arg1, TargetReg(kArg1, arg1)); 337 if (arg2.wide == 0) { 338 LoadValueDirectFixed(arg2, TargetReg(kArg2, arg2)); 339 } else { 340 LoadValueDirectWideFixed(arg2, TargetReg(kArg2, kWide)); 341 } 342 LoadConstant(TargetReg(kArg0, kNotWide), arg0); 343 ClobberCallerSave(); 344 CallHelper(r_tgt, trampoline, safepoint_pc); 345 } 346 347 void Mir2Lir::CallRuntimeHelperRegLocationRegLocationRegLocation( 348 QuickEntrypointEnum trampoline, 349 RegLocation arg0, 350 RegLocation arg1, 351 RegLocation arg2, 352 bool safepoint_pc) { 353 RegStorage r_tgt = CallHelperSetup(trampoline); 354 LoadValueDirectFixed(arg0, TargetReg(kArg0, arg0)); 355 LoadValueDirectFixed(arg1, TargetReg(kArg1, arg1)); 356 LoadValueDirectFixed(arg2, TargetReg(kArg2, arg2)); 357 ClobberCallerSave(); 358 CallHelper(r_tgt, trampoline, safepoint_pc); 359 } 360 361 /* 362 * If there are any ins passed in registers that have not been promoted 363 * to a callee-save register, flush them to the frame. Perform initial 364 * assignment of promoted arguments. 365 * 366 * ArgLocs is an array of location records describing the incoming arguments 367 * with one location record per word of argument. 368 */ 369 void Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { 370 /* 371 * Dummy up a RegLocation for the incoming StackReference<mirror::ArtMethod> 372 * It will attempt to keep kArg0 live (or copy it to home location 373 * if promoted). 374 */ 375 RegLocation rl_src = rl_method; 376 rl_src.location = kLocPhysReg; 377 rl_src.reg = TargetReg(kArg0, kRef); 378 rl_src.home = false; 379 MarkLive(rl_src); 380 StoreValue(rl_method, rl_src); 381 // If Method* has been promoted, explicitly flush 382 if (rl_method.location == kLocPhysReg) { 383 StoreRefDisp(TargetPtrReg(kSp), 0, rl_src.reg, kNotVolatile); 384 } 385 386 if (cu_->num_ins == 0) { 387 return; 388 } 389 390 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 391 /* 392 * Copy incoming arguments to their proper home locations. 393 * NOTE: an older version of dx had an issue in which 394 * it would reuse static method argument registers. 395 * This could result in the same Dalvik virtual register 396 * being promoted to both core and fp regs. To account for this, 397 * we only copy to the corresponding promoted physical register 398 * if it matches the type of the SSA name for the incoming 399 * argument. It is also possible that long and double arguments 400 * end up half-promoted. In those cases, we must flush the promoted 401 * half to memory as well. 402 */ 403 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 404 for (int i = 0; i < cu_->num_ins; i++) { 405 PromotionMap* v_map = &promotion_map_[start_vreg + i]; 406 RegStorage reg = GetArgMappingToPhysicalReg(i); 407 408 if (reg.Valid()) { 409 // If arriving in register 410 bool need_flush = true; 411 RegLocation* t_loc = &ArgLocs[i]; 412 if ((v_map->core_location == kLocPhysReg) && !t_loc->fp) { 413 OpRegCopy(RegStorage::Solo32(v_map->core_reg), reg); 414 need_flush = false; 415 } else if ((v_map->fp_location == kLocPhysReg) && t_loc->fp) { 416 OpRegCopy(RegStorage::Solo32(v_map->fp_reg), reg); 417 need_flush = false; 418 } else { 419 need_flush = true; 420 } 421 422 // For wide args, force flush if not fully promoted 423 if (t_loc->wide) { 424 PromotionMap* p_map = v_map + (t_loc->high_word ? -1 : +1); 425 // Is only half promoted? 426 need_flush |= (p_map->core_location != v_map->core_location) || 427 (p_map->fp_location != v_map->fp_location); 428 if ((cu_->instruction_set == kThumb2) && t_loc->fp && !need_flush) { 429 /* 430 * In Arm, a double is represented as a pair of consecutive single float 431 * registers starting at an even number. It's possible that both Dalvik vRegs 432 * representing the incoming double were independently promoted as singles - but 433 * not in a form usable as a double. If so, we need to flush - even though the 434 * incoming arg appears fully in register. At this point in the code, both 435 * halves of the double are promoted. Make sure they are in a usable form. 436 */ 437 int lowreg_index = start_vreg + i + (t_loc->high_word ? -1 : 0); 438 int low_reg = promotion_map_[lowreg_index].fp_reg; 439 int high_reg = promotion_map_[lowreg_index + 1].fp_reg; 440 if (((low_reg & 0x1) != 0) || (high_reg != (low_reg + 1))) { 441 need_flush = true; 442 } 443 } 444 } 445 if (need_flush) { 446 Store32Disp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), reg); 447 } 448 } else { 449 // If arriving in frame & promoted 450 if (v_map->core_location == kLocPhysReg) { 451 Load32Disp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), 452 RegStorage::Solo32(v_map->core_reg)); 453 } 454 if (v_map->fp_location == kLocPhysReg) { 455 Load32Disp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), 456 RegStorage::Solo32(v_map->fp_reg)); 457 } 458 } 459 } 460 } 461 462 static void CommonCallCodeLoadThisIntoArg1(const CallInfo* info, Mir2Lir* cg) { 463 RegLocation rl_arg = info->args[0]; 464 cg->LoadValueDirectFixed(rl_arg, cg->TargetReg(kArg1, kRef)); 465 } 466 467 static void CommonCallCodeLoadClassIntoArg0(const CallInfo* info, Mir2Lir* cg) { 468 cg->GenNullCheck(cg->TargetReg(kArg1, kRef), info->opt_flags); 469 // get this->klass_ [use kArg1, set kArg0] 470 cg->LoadRefDisp(cg->TargetReg(kArg1, kRef), mirror::Object::ClassOffset().Int32Value(), 471 cg->TargetReg(kArg0, kRef), 472 kNotVolatile); 473 cg->MarkPossibleNullPointerException(info->opt_flags); 474 } 475 476 static bool CommonCallCodeLoadCodePointerIntoInvokeTgt(const CallInfo* info, 477 const RegStorage* alt_from, 478 const CompilationUnit* cu, Mir2Lir* cg) { 479 if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 480 int32_t offset = mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset( 481 InstructionSetPointerSize(cu->instruction_set)).Int32Value(); 482 // Get the compiled code address [use *alt_from or kArg0, set kInvokeTgt] 483 cg->LoadWordDisp(alt_from == nullptr ? cg->TargetReg(kArg0, kRef) : *alt_from, offset, 484 cg->TargetPtrReg(kInvokeTgt)); 485 return true; 486 } 487 return false; 488 } 489 490 /* 491 * Bit of a hack here - in the absence of a real scheduling pass, 492 * emit the next instruction in static & direct invoke sequences. 493 */ 494 static int NextSDCallInsn(CompilationUnit* cu, CallInfo* info, 495 int state, const MethodReference& target_method, 496 uint32_t unused, 497 uintptr_t direct_code, uintptr_t direct_method, 498 InvokeType type) { 499 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 500 if (direct_code != 0 && direct_method != 0) { 501 switch (state) { 502 case 0: // Get the current Method* [sets kArg0] 503 if (direct_code != static_cast<uintptr_t>(-1)) { 504 if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 505 cg->LoadConstant(cg->TargetPtrReg(kInvokeTgt), direct_code); 506 } 507 } else if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 508 cg->LoadCodeAddress(target_method, type, kInvokeTgt); 509 } 510 if (direct_method != static_cast<uintptr_t>(-1)) { 511 cg->LoadConstant(cg->TargetReg(kArg0, kRef), direct_method); 512 } else { 513 cg->LoadMethodAddress(target_method, type, kArg0); 514 } 515 break; 516 default: 517 return -1; 518 } 519 } else { 520 RegStorage arg0_ref = cg->TargetReg(kArg0, kRef); 521 switch (state) { 522 case 0: // Get the current Method* [sets kArg0] 523 // TUNING: we can save a reg copy if Method* has been promoted. 524 cg->LoadCurrMethodDirect(arg0_ref); 525 break; 526 case 1: // Get method->dex_cache_resolved_methods_ 527 cg->LoadRefDisp(arg0_ref, 528 mirror::ArtMethod::DexCacheResolvedMethodsOffset().Int32Value(), 529 arg0_ref, 530 kNotVolatile); 531 // Set up direct code if known. 532 if (direct_code != 0) { 533 if (direct_code != static_cast<uintptr_t>(-1)) { 534 cg->LoadConstant(cg->TargetPtrReg(kInvokeTgt), direct_code); 535 } else if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 536 CHECK_LT(target_method.dex_method_index, target_method.dex_file->NumMethodIds()); 537 cg->LoadCodeAddress(target_method, type, kInvokeTgt); 538 } 539 } 540 break; 541 case 2: // Grab target method* 542 CHECK_EQ(cu->dex_file, target_method.dex_file); 543 cg->LoadRefDisp(arg0_ref, 544 ObjArray::OffsetOfElement(target_method.dex_method_index).Int32Value(), 545 arg0_ref, 546 kNotVolatile); 547 break; 548 case 3: // Grab the code from the method* 549 if (direct_code == 0) { 550 if (CommonCallCodeLoadCodePointerIntoInvokeTgt(info, &arg0_ref, cu, cg)) { 551 break; // kInvokeTgt := arg0_ref->entrypoint 552 } 553 } else if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 554 break; 555 } 556 // Intentional fallthrough for x86 557 default: 558 return -1; 559 } 560 } 561 return state + 1; 562 } 563 564 /* 565 * Bit of a hack here - in the absence of a real scheduling pass, 566 * emit the next instruction in a virtual invoke sequence. 567 * We can use kLr as a temp prior to target address loading 568 * Note also that we'll load the first argument ("this") into 569 * kArg1 here rather than the standard LoadArgRegs. 570 */ 571 static int NextVCallInsn(CompilationUnit* cu, CallInfo* info, 572 int state, const MethodReference& target_method, 573 uint32_t method_idx, uintptr_t unused, uintptr_t unused2, 574 InvokeType unused3) { 575 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 576 /* 577 * This is the fast path in which the target virtual method is 578 * fully resolved at compile time. 579 */ 580 switch (state) { 581 case 0: 582 CommonCallCodeLoadThisIntoArg1(info, cg); // kArg1 := this 583 break; 584 case 1: 585 CommonCallCodeLoadClassIntoArg0(info, cg); // kArg0 := kArg1->class 586 // Includes a null-check. 587 break; 588 case 2: { 589 // Get this->klass_.embedded_vtable[method_idx] [usr kArg0, set kArg0] 590 int32_t offset = mirror::Class::EmbeddedVTableOffset().Uint32Value() + 591 method_idx * sizeof(mirror::Class::VTableEntry); 592 // Load target method from embedded vtable to kArg0 [use kArg0, set kArg0] 593 cg->LoadRefDisp(cg->TargetReg(kArg0, kRef), offset, cg->TargetReg(kArg0, kRef), kNotVolatile); 594 break; 595 } 596 case 3: 597 if (CommonCallCodeLoadCodePointerIntoInvokeTgt(info, nullptr, cu, cg)) { 598 break; // kInvokeTgt := kArg0->entrypoint 599 } 600 // Intentional fallthrough for X86 601 default: 602 return -1; 603 } 604 return state + 1; 605 } 606 607 /* 608 * Emit the next instruction in an invoke interface sequence. This will do a lookup in the 609 * class's IMT, calling either the actual method or art_quick_imt_conflict_trampoline if 610 * more than one interface method map to the same index. Note also that we'll load the first 611 * argument ("this") into kArg1 here rather than the standard LoadArgRegs. 612 */ 613 static int NextInterfaceCallInsn(CompilationUnit* cu, CallInfo* info, int state, 614 const MethodReference& target_method, 615 uint32_t method_idx, uintptr_t unused, 616 uintptr_t direct_method, InvokeType unused2) { 617 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 618 619 switch (state) { 620 case 0: // Set target method index in case of conflict [set kHiddenArg, kHiddenFpArg (x86)] 621 CHECK_LT(target_method.dex_method_index, target_method.dex_file->NumMethodIds()); 622 cg->LoadConstant(cg->TargetReg(kHiddenArg, kNotWide), target_method.dex_method_index); 623 if (cu->instruction_set == kX86) { 624 cg->OpRegCopy(cg->TargetReg(kHiddenFpArg, kNotWide), cg->TargetReg(kHiddenArg, kNotWide)); 625 } 626 break; 627 case 1: 628 CommonCallCodeLoadThisIntoArg1(info, cg); // kArg1 := this 629 break; 630 case 2: 631 CommonCallCodeLoadClassIntoArg0(info, cg); // kArg0 := kArg1->class 632 // Includes a null-check. 633 break; 634 case 3: { // Get target method [use kInvokeTgt, set kArg0] 635 int32_t offset = mirror::Class::EmbeddedImTableOffset().Uint32Value() + 636 (method_idx % mirror::Class::kImtSize) * sizeof(mirror::Class::ImTableEntry); 637 // Load target method from embedded imtable to kArg0 [use kArg0, set kArg0] 638 cg->LoadRefDisp(cg->TargetReg(kArg0, kRef), offset, cg->TargetReg(kArg0, kRef), kNotVolatile); 639 break; 640 } 641 case 4: 642 if (CommonCallCodeLoadCodePointerIntoInvokeTgt(info, nullptr, cu, cg)) { 643 break; // kInvokeTgt := kArg0->entrypoint 644 } 645 // Intentional fallthrough for X86 646 default: 647 return -1; 648 } 649 return state + 1; 650 } 651 652 static int NextInvokeInsnSP(CompilationUnit* cu, CallInfo* info, 653 QuickEntrypointEnum trampoline, int state, 654 const MethodReference& target_method, uint32_t method_idx) { 655 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 656 657 658 /* 659 * This handles the case in which the base method is not fully 660 * resolved at compile time, we bail to a runtime helper. 661 */ 662 if (state == 0) { 663 if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 664 // Load trampoline target 665 int32_t disp; 666 if (cu->target64) { 667 disp = GetThreadOffset<8>(trampoline).Int32Value(); 668 } else { 669 disp = GetThreadOffset<4>(trampoline).Int32Value(); 670 } 671 cg->LoadWordDisp(cg->TargetPtrReg(kSelf), disp, cg->TargetPtrReg(kInvokeTgt)); 672 } 673 // Load kArg0 with method index 674 CHECK_EQ(cu->dex_file, target_method.dex_file); 675 cg->LoadConstant(cg->TargetReg(kArg0, kNotWide), target_method.dex_method_index); 676 return 1; 677 } 678 return -1; 679 } 680 681 static int NextStaticCallInsnSP(CompilationUnit* cu, CallInfo* info, 682 int state, 683 const MethodReference& target_method, 684 uint32_t unused, uintptr_t unused2, 685 uintptr_t unused3, InvokeType unused4) { 686 return NextInvokeInsnSP(cu, info, kQuickInvokeStaticTrampolineWithAccessCheck, state, 687 target_method, 0); 688 } 689 690 static int NextDirectCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, 691 const MethodReference& target_method, 692 uint32_t unused, uintptr_t unused2, 693 uintptr_t unused3, InvokeType unused4) { 694 return NextInvokeInsnSP(cu, info, kQuickInvokeDirectTrampolineWithAccessCheck, state, 695 target_method, 0); 696 } 697 698 static int NextSuperCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, 699 const MethodReference& target_method, 700 uint32_t unused, uintptr_t unused2, 701 uintptr_t unused3, InvokeType unused4) { 702 return NextInvokeInsnSP(cu, info, kQuickInvokeSuperTrampolineWithAccessCheck, state, 703 target_method, 0); 704 } 705 706 static int NextVCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, 707 const MethodReference& target_method, 708 uint32_t unused, uintptr_t unused2, 709 uintptr_t unused3, InvokeType unused4) { 710 return NextInvokeInsnSP(cu, info, kQuickInvokeVirtualTrampolineWithAccessCheck, state, 711 target_method, 0); 712 } 713 714 static int NextInterfaceCallInsnWithAccessCheck(CompilationUnit* cu, 715 CallInfo* info, int state, 716 const MethodReference& target_method, 717 uint32_t unused, uintptr_t unused2, 718 uintptr_t unused3, InvokeType unused4) { 719 return NextInvokeInsnSP(cu, info, kQuickInvokeInterfaceTrampolineWithAccessCheck, state, 720 target_method, 0); 721 } 722 723 int Mir2Lir::LoadArgRegs(CallInfo* info, int call_state, 724 NextCallInsn next_call_insn, 725 const MethodReference& target_method, 726 uint32_t vtable_idx, uintptr_t direct_code, 727 uintptr_t direct_method, InvokeType type, bool skip_this) { 728 int last_arg_reg = 3 - 1; 729 int arg_regs[3] = {TargetReg(kArg1, kNotWide).GetReg(), TargetReg(kArg2, kNotWide).GetReg(), 730 TargetReg(kArg3, kNotWide).GetReg()}; 731 732 int next_reg = 0; 733 int next_arg = 0; 734 if (skip_this) { 735 next_reg++; 736 next_arg++; 737 } 738 for (; (next_reg <= last_arg_reg) && (next_arg < info->num_arg_words); next_reg++) { 739 RegLocation rl_arg = info->args[next_arg++]; 740 rl_arg = UpdateRawLoc(rl_arg); 741 if (rl_arg.wide && (next_reg <= last_arg_reg - 1)) { 742 RegStorage r_tmp(RegStorage::k64BitPair, arg_regs[next_reg], arg_regs[next_reg + 1]); 743 LoadValueDirectWideFixed(rl_arg, r_tmp); 744 next_reg++; 745 next_arg++; 746 } else { 747 if (rl_arg.wide) { 748 rl_arg = NarrowRegLoc(rl_arg); 749 rl_arg.is_const = false; 750 } 751 LoadValueDirectFixed(rl_arg, RegStorage::Solo32(arg_regs[next_reg])); 752 } 753 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 754 direct_code, direct_method, type); 755 } 756 return call_state; 757 } 758 759 /* 760 * Load up to 5 arguments, the first three of which will be in 761 * kArg1 .. kArg3. On entry kArg0 contains the current method pointer, 762 * and as part of the load sequence, it must be replaced with 763 * the target method pointer. Note, this may also be called 764 * for "range" variants if the number of arguments is 5 or fewer. 765 */ 766 int Mir2Lir::GenDalvikArgsNoRange(CallInfo* info, 767 int call_state, LIR** pcrLabel, NextCallInsn next_call_insn, 768 const MethodReference& target_method, 769 uint32_t vtable_idx, uintptr_t direct_code, 770 uintptr_t direct_method, InvokeType type, bool skip_this) { 771 RegLocation rl_arg; 772 773 /* If no arguments, just return */ 774 if (info->num_arg_words == 0) 775 return call_state; 776 777 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 778 direct_code, direct_method, type); 779 780 DCHECK_LE(info->num_arg_words, 5); 781 if (info->num_arg_words > 3) { 782 int32_t next_use = 3; 783 // Detect special case of wide arg spanning arg3/arg4 784 RegLocation rl_use0 = info->args[0]; 785 RegLocation rl_use1 = info->args[1]; 786 RegLocation rl_use2 = info->args[2]; 787 if (((!rl_use0.wide && !rl_use1.wide) || rl_use0.wide) && rl_use2.wide) { 788 RegStorage reg; 789 // Wide spans, we need the 2nd half of uses[2]. 790 rl_arg = UpdateLocWide(rl_use2); 791 if (rl_arg.location == kLocPhysReg) { 792 if (rl_arg.reg.IsPair()) { 793 reg = rl_arg.reg.GetHigh(); 794 } else { 795 RegisterInfo* info = GetRegInfo(rl_arg.reg); 796 info = info->FindMatchingView(RegisterInfo::kHighSingleStorageMask); 797 if (info == nullptr) { 798 // NOTE: For hard float convention we won't split arguments across reg/mem. 799 UNIMPLEMENTED(FATAL) << "Needs hard float api."; 800 } 801 reg = info->GetReg(); 802 } 803 } else { 804 // kArg2 & rArg3 can safely be used here 805 reg = TargetReg(kArg3, kNotWide); 806 { 807 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 808 Load32Disp(TargetPtrReg(kSp), SRegOffset(rl_arg.s_reg_low) + 4, reg); 809 } 810 call_state = next_call_insn(cu_, info, call_state, target_method, 811 vtable_idx, direct_code, direct_method, type); 812 } 813 { 814 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 815 Store32Disp(TargetPtrReg(kSp), (next_use + 1) * 4, reg); 816 } 817 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 818 direct_code, direct_method, type); 819 next_use++; 820 } 821 // Loop through the rest 822 while (next_use < info->num_arg_words) { 823 RegStorage arg_reg; 824 rl_arg = info->args[next_use]; 825 rl_arg = UpdateRawLoc(rl_arg); 826 if (rl_arg.location == kLocPhysReg) { 827 arg_reg = rl_arg.reg; 828 } else { 829 arg_reg = TargetReg(kArg2, rl_arg.wide ? kWide : kNotWide); 830 if (rl_arg.wide) { 831 LoadValueDirectWideFixed(rl_arg, arg_reg); 832 } else { 833 LoadValueDirectFixed(rl_arg, arg_reg); 834 } 835 call_state = next_call_insn(cu_, info, call_state, target_method, 836 vtable_idx, direct_code, direct_method, type); 837 } 838 int outs_offset = (next_use + 1) * 4; 839 { 840 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 841 if (rl_arg.wide) { 842 StoreBaseDisp(TargetPtrReg(kSp), outs_offset, arg_reg, k64, kNotVolatile); 843 next_use += 2; 844 } else { 845 Store32Disp(TargetPtrReg(kSp), outs_offset, arg_reg); 846 next_use++; 847 } 848 } 849 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 850 direct_code, direct_method, type); 851 } 852 } 853 854 call_state = LoadArgRegs(info, call_state, next_call_insn, 855 target_method, vtable_idx, direct_code, direct_method, 856 type, skip_this); 857 858 if (pcrLabel) { 859 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 860 *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags); 861 } else { 862 *pcrLabel = nullptr; 863 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && 864 (info->opt_flags & MIR_IGNORE_NULL_CHECK)) { 865 return call_state; 866 } 867 // In lieu of generating a check for kArg1 being null, we need to 868 // perform a load when doing implicit checks. 869 GenImplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags); 870 } 871 } 872 return call_state; 873 } 874 875 // Default implementation of implicit null pointer check. 876 // Overridden by arch specific as necessary. 877 void Mir2Lir::GenImplicitNullCheck(RegStorage reg, int opt_flags) { 878 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 879 return; 880 } 881 RegStorage tmp = AllocTemp(); 882 Load32Disp(reg, 0, tmp); 883 MarkPossibleNullPointerException(opt_flags); 884 FreeTemp(tmp); 885 } 886 887 888 /* 889 * May have 0+ arguments (also used for jumbo). Note that 890 * source virtual registers may be in physical registers, so may 891 * need to be flushed to home location before copying. This 892 * applies to arg3 and above (see below). 893 * 894 * Two general strategies: 895 * If < 20 arguments 896 * Pass args 3-18 using vldm/vstm block copy 897 * Pass arg0, arg1 & arg2 in kArg1-kArg3 898 * If 20+ arguments 899 * Pass args arg19+ using memcpy block copy 900 * Pass arg0, arg1 & arg2 in kArg1-kArg3 901 * 902 */ 903 int Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state, 904 LIR** pcrLabel, NextCallInsn next_call_insn, 905 const MethodReference& target_method, 906 uint32_t vtable_idx, uintptr_t direct_code, uintptr_t direct_method, 907 InvokeType type, bool skip_this) { 908 // If we can treat it as non-range (Jumbo ops will use range form) 909 if (info->num_arg_words <= 5) 910 return GenDalvikArgsNoRange(info, call_state, pcrLabel, 911 next_call_insn, target_method, vtable_idx, 912 direct_code, direct_method, type, skip_this); 913 /* 914 * First load the non-register arguments. Both forms expect all 915 * of the source arguments to be in their home frame location, so 916 * scan the s_reg names and flush any that have been promoted to 917 * frame backing storage. 918 */ 919 // Scan the rest of the args - if in phys_reg flush to memory 920 for (int next_arg = 0; next_arg < info->num_arg_words;) { 921 RegLocation loc = info->args[next_arg]; 922 if (loc.wide) { 923 loc = UpdateLocWide(loc); 924 if ((next_arg >= 2) && (loc.location == kLocPhysReg)) { 925 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 926 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); 927 } 928 next_arg += 2; 929 } else { 930 loc = UpdateLoc(loc); 931 if ((next_arg >= 3) && (loc.location == kLocPhysReg)) { 932 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 933 Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); 934 } 935 next_arg++; 936 } 937 } 938 939 // Logic below assumes that Method pointer is at offset zero from SP. 940 DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0); 941 942 // The first 3 arguments are passed via registers. 943 // TODO: For 64-bit, instead of hardcoding 4 for Method* size, we should either 944 // get size of uintptr_t or size of object reference according to model being used. 945 int outs_offset = 4 /* Method* */ + (3 * sizeof(uint32_t)); 946 int start_offset = SRegOffset(info->args[3].s_reg_low); 947 int regs_left_to_pass_via_stack = info->num_arg_words - 3; 948 DCHECK_GT(regs_left_to_pass_via_stack, 0); 949 950 if (cu_->instruction_set == kThumb2 && regs_left_to_pass_via_stack <= 16) { 951 // Use vldm/vstm pair using kArg3 as a temp 952 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 953 direct_code, direct_method, type); 954 OpRegRegImm(kOpAdd, TargetReg(kArg3, kRef), TargetPtrReg(kSp), start_offset); 955 LIR* ld = nullptr; 956 { 957 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 958 ld = OpVldm(TargetReg(kArg3, kRef), regs_left_to_pass_via_stack); 959 } 960 // TUNING: loosen barrier 961 ld->u.m.def_mask = &kEncodeAll; 962 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 963 direct_code, direct_method, type); 964 OpRegRegImm(kOpAdd, TargetReg(kArg3, kRef), TargetPtrReg(kSp), 4 /* Method* */ + (3 * 4)); 965 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 966 direct_code, direct_method, type); 967 LIR* st = nullptr; 968 { 969 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 970 st = OpVstm(TargetReg(kArg3, kRef), regs_left_to_pass_via_stack); 971 } 972 st->u.m.def_mask = &kEncodeAll; 973 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 974 direct_code, direct_method, type); 975 } else if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 976 int current_src_offset = start_offset; 977 int current_dest_offset = outs_offset; 978 979 // Only davik regs are accessed in this loop; no next_call_insn() calls. 980 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 981 while (regs_left_to_pass_via_stack > 0) { 982 // This is based on the knowledge that the stack itself is 16-byte aligned. 983 bool src_is_16b_aligned = (current_src_offset & 0xF) == 0; 984 bool dest_is_16b_aligned = (current_dest_offset & 0xF) == 0; 985 size_t bytes_to_move; 986 987 /* 988 * The amount to move defaults to 32-bit. If there are 4 registers left to move, then do a 989 * a 128-bit move because we won't get the chance to try to aligned. If there are more than 990 * 4 registers left to move, consider doing a 128-bit only if either src or dest are aligned. 991 * We do this because we could potentially do a smaller move to align. 992 */ 993 if (regs_left_to_pass_via_stack == 4 || 994 (regs_left_to_pass_via_stack > 4 && (src_is_16b_aligned || dest_is_16b_aligned))) { 995 // Moving 128-bits via xmm register. 996 bytes_to_move = sizeof(uint32_t) * 4; 997 998 // Allocate a free xmm temp. Since we are working through the calling sequence, 999 // we expect to have an xmm temporary available. AllocTempDouble will abort if 1000 // there are no free registers. 1001 RegStorage temp = AllocTempDouble(); 1002 1003 LIR* ld1 = nullptr; 1004 LIR* ld2 = nullptr; 1005 LIR* st1 = nullptr; 1006 LIR* st2 = nullptr; 1007 1008 /* 1009 * The logic is similar for both loads and stores. If we have 16-byte alignment, 1010 * do an aligned move. If we have 8-byte alignment, then do the move in two 1011 * parts. This approach prevents possible cache line splits. Finally, fall back 1012 * to doing an unaligned move. In most cases we likely won't split the cache 1013 * line but we cannot prove it and thus take a conservative approach. 1014 */ 1015 bool src_is_8b_aligned = (current_src_offset & 0x7) == 0; 1016 bool dest_is_8b_aligned = (current_dest_offset & 0x7) == 0; 1017 1018 if (src_is_16b_aligned) { 1019 ld1 = OpMovRegMem(temp, TargetPtrReg(kSp), current_src_offset, kMovA128FP); 1020 } else if (src_is_8b_aligned) { 1021 ld1 = OpMovRegMem(temp, TargetPtrReg(kSp), current_src_offset, kMovLo128FP); 1022 ld2 = OpMovRegMem(temp, TargetPtrReg(kSp), current_src_offset + (bytes_to_move >> 1), 1023 kMovHi128FP); 1024 } else { 1025 ld1 = OpMovRegMem(temp, TargetPtrReg(kSp), current_src_offset, kMovU128FP); 1026 } 1027 1028 if (dest_is_16b_aligned) { 1029 st1 = OpMovMemReg(TargetPtrReg(kSp), current_dest_offset, temp, kMovA128FP); 1030 } else if (dest_is_8b_aligned) { 1031 st1 = OpMovMemReg(TargetPtrReg(kSp), current_dest_offset, temp, kMovLo128FP); 1032 st2 = OpMovMemReg(TargetPtrReg(kSp), current_dest_offset + (bytes_to_move >> 1), 1033 temp, kMovHi128FP); 1034 } else { 1035 st1 = OpMovMemReg(TargetPtrReg(kSp), current_dest_offset, temp, kMovU128FP); 1036 } 1037 1038 // TODO If we could keep track of aliasing information for memory accesses that are wider 1039 // than 64-bit, we wouldn't need to set up a barrier. 1040 if (ld1 != nullptr) { 1041 if (ld2 != nullptr) { 1042 // For 64-bit load we can actually set up the aliasing information. 1043 AnnotateDalvikRegAccess(ld1, current_src_offset >> 2, true, true); 1044 AnnotateDalvikRegAccess(ld2, (current_src_offset + (bytes_to_move >> 1)) >> 2, true, 1045 true); 1046 } else { 1047 // Set barrier for 128-bit load. 1048 ld1->u.m.def_mask = &kEncodeAll; 1049 } 1050 } 1051 if (st1 != nullptr) { 1052 if (st2 != nullptr) { 1053 // For 64-bit store we can actually set up the aliasing information. 1054 AnnotateDalvikRegAccess(st1, current_dest_offset >> 2, false, true); 1055 AnnotateDalvikRegAccess(st2, (current_dest_offset + (bytes_to_move >> 1)) >> 2, false, 1056 true); 1057 } else { 1058 // Set barrier for 128-bit store. 1059 st1->u.m.def_mask = &kEncodeAll; 1060 } 1061 } 1062 1063 // Free the temporary used for the data movement. 1064 FreeTemp(temp); 1065 } else { 1066 // Moving 32-bits via general purpose register. 1067 bytes_to_move = sizeof(uint32_t); 1068 1069 // Instead of allocating a new temp, simply reuse one of the registers being used 1070 // for argument passing. 1071 RegStorage temp = TargetReg(kArg3, kNotWide); 1072 1073 // Now load the argument VR and store to the outs. 1074 Load32Disp(TargetPtrReg(kSp), current_src_offset, temp); 1075 Store32Disp(TargetPtrReg(kSp), current_dest_offset, temp); 1076 } 1077 1078 current_src_offset += bytes_to_move; 1079 current_dest_offset += bytes_to_move; 1080 regs_left_to_pass_via_stack -= (bytes_to_move >> 2); 1081 } 1082 } else { 1083 // Generate memcpy 1084 OpRegRegImm(kOpAdd, TargetReg(kArg0, kRef), TargetPtrReg(kSp), outs_offset); 1085 OpRegRegImm(kOpAdd, TargetReg(kArg1, kRef), TargetPtrReg(kSp), start_offset); 1086 CallRuntimeHelperRegRegImm(kQuickMemcpy, TargetReg(kArg0, kRef), TargetReg(kArg1, kRef), 1087 (info->num_arg_words - 3) * 4, false); 1088 } 1089 1090 call_state = LoadArgRegs(info, call_state, next_call_insn, 1091 target_method, vtable_idx, direct_code, direct_method, 1092 type, skip_this); 1093 1094 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 1095 direct_code, direct_method, type); 1096 if (pcrLabel) { 1097 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 1098 *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags); 1099 } else { 1100 *pcrLabel = nullptr; 1101 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && 1102 (info->opt_flags & MIR_IGNORE_NULL_CHECK)) { 1103 return call_state; 1104 } 1105 // In lieu of generating a check for kArg1 being null, we need to 1106 // perform a load when doing implicit checks. 1107 GenImplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags); 1108 } 1109 } 1110 return call_state; 1111 } 1112 1113 RegLocation Mir2Lir::InlineTarget(CallInfo* info) { 1114 RegLocation res; 1115 if (info->result.location == kLocInvalid) { 1116 res = GetReturn(LocToRegClass(info->result)); 1117 } else { 1118 res = info->result; 1119 } 1120 return res; 1121 } 1122 1123 RegLocation Mir2Lir::InlineTargetWide(CallInfo* info) { 1124 RegLocation res; 1125 if (info->result.location == kLocInvalid) { 1126 res = GetReturnWide(kCoreReg); 1127 } else { 1128 res = info->result; 1129 } 1130 return res; 1131 } 1132 1133 bool Mir2Lir::GenInlinedReferenceGetReferent(CallInfo* info) { 1134 if (cu_->instruction_set == kMips) { 1135 // TODO - add Mips implementation 1136 return false; 1137 } 1138 1139 // the refrence class is stored in the image dex file which might not be the same as the cu's 1140 // dex file. Query the reference class for the image dex file then reset to starting dex file 1141 // in after loading class type. 1142 uint16_t type_idx = 0; 1143 const DexFile* ref_dex_file = nullptr; 1144 { 1145 ScopedObjectAccess soa(Thread::Current()); 1146 type_idx = mirror::Reference::GetJavaLangRefReference()->GetDexTypeIndex(); 1147 ref_dex_file = mirror::Reference::GetJavaLangRefReference()->GetDexCache()->GetDexFile(); 1148 } 1149 CHECK(LIKELY(ref_dex_file != nullptr)); 1150 1151 // address is either static within the image file, or needs to be patched up after compilation. 1152 bool unused_type_initialized; 1153 bool use_direct_type_ptr; 1154 uintptr_t direct_type_ptr; 1155 bool is_finalizable; 1156 const DexFile* old_dex = cu_->dex_file; 1157 cu_->dex_file = ref_dex_file; 1158 RegStorage reg_class = TargetReg(kArg1, kRef); 1159 Clobber(reg_class); 1160 LockTemp(reg_class); 1161 if (!cu_->compiler_driver->CanEmbedTypeInCode(*ref_dex_file, type_idx, &unused_type_initialized, 1162 &use_direct_type_ptr, &direct_type_ptr, 1163 &is_finalizable) || is_finalizable) { 1164 cu_->dex_file = old_dex; 1165 // address is not known and post-compile patch is not possible, cannot insert intrinsic. 1166 return false; 1167 } 1168 if (use_direct_type_ptr) { 1169 LoadConstant(reg_class, direct_type_ptr); 1170 } else if (cu_->dex_file == old_dex) { 1171 // TODO: Bug 16656190 If cu_->dex_file != old_dex the patching could retrieve the wrong class 1172 // since the load class is indexed only by the type_idx. We should include which dex file a 1173 // class is from in the LoadClassType LIR. 1174 LoadClassType(type_idx, kArg1); 1175 } else { 1176 cu_->dex_file = old_dex; 1177 return false; 1178 } 1179 cu_->dex_file = old_dex; 1180 1181 // get the offset for flags in reference class. 1182 uint32_t slow_path_flag_offset = 0; 1183 uint32_t disable_flag_offset = 0; 1184 { 1185 ScopedObjectAccess soa(Thread::Current()); 1186 mirror::Class* reference_class = mirror::Reference::GetJavaLangRefReference(); 1187 slow_path_flag_offset = reference_class->GetSlowPathFlagOffset().Uint32Value(); 1188 disable_flag_offset = reference_class->GetDisableIntrinsicFlagOffset().Uint32Value(); 1189 } 1190 CHECK(slow_path_flag_offset && disable_flag_offset && 1191 (slow_path_flag_offset != disable_flag_offset)); 1192 1193 // intrinsic logic start. 1194 RegLocation rl_obj = info->args[0]; 1195 rl_obj = LoadValue(rl_obj); 1196 1197 RegStorage reg_slow_path = AllocTemp(); 1198 RegStorage reg_disabled = AllocTemp(); 1199 Load32Disp(reg_class, slow_path_flag_offset, reg_slow_path); 1200 Load32Disp(reg_class, disable_flag_offset, reg_disabled); 1201 FreeTemp(reg_class); 1202 LIR* or_inst = OpRegRegReg(kOpOr, reg_slow_path, reg_slow_path, reg_disabled); 1203 FreeTemp(reg_disabled); 1204 1205 // if slow path, jump to JNI path target 1206 LIR* slow_path_branch; 1207 if (or_inst->u.m.def_mask->HasBit(ResourceMask::kCCode)) { 1208 // Generate conditional branch only, as the OR set a condition state (we are interested in a 'Z' flag). 1209 slow_path_branch = OpCondBranch(kCondNe, nullptr); 1210 } else { 1211 // Generate compare and branch. 1212 slow_path_branch = OpCmpImmBranch(kCondNe, reg_slow_path, 0, nullptr); 1213 } 1214 FreeTemp(reg_slow_path); 1215 1216 // slow path not enabled, simply load the referent of the reference object 1217 RegLocation rl_dest = InlineTarget(info); 1218 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 1219 GenNullCheck(rl_obj.reg, info->opt_flags); 1220 LoadRefDisp(rl_obj.reg, mirror::Reference::ReferentOffset().Int32Value(), rl_result.reg, 1221 kNotVolatile); 1222 MarkPossibleNullPointerException(info->opt_flags); 1223 StoreValue(rl_dest, rl_result); 1224 1225 LIR* intrinsic_finish = NewLIR0(kPseudoTargetLabel); 1226 AddIntrinsicSlowPath(info, slow_path_branch, intrinsic_finish); 1227 ClobberCallerSave(); // We must clobber everything because slow path will return here 1228 return true; 1229 } 1230 1231 bool Mir2Lir::GenInlinedCharAt(CallInfo* info) { 1232 if (cu_->instruction_set == kMips) { 1233 // TODO - add Mips implementation 1234 return false; 1235 } 1236 // Location of reference to data array 1237 int value_offset = mirror::String::ValueOffset().Int32Value(); 1238 // Location of count 1239 int count_offset = mirror::String::CountOffset().Int32Value(); 1240 // Starting offset within data array 1241 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 1242 // Start of char data with array_ 1243 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 1244 1245 RegLocation rl_obj = info->args[0]; 1246 RegLocation rl_idx = info->args[1]; 1247 rl_obj = LoadValue(rl_obj, kRefReg); 1248 rl_idx = LoadValue(rl_idx, kCoreReg); 1249 RegStorage reg_max; 1250 GenNullCheck(rl_obj.reg, info->opt_flags); 1251 bool range_check = (!(info->opt_flags & MIR_IGNORE_RANGE_CHECK)); 1252 LIR* range_check_branch = nullptr; 1253 RegStorage reg_off; 1254 RegStorage reg_ptr; 1255 reg_off = AllocTemp(); 1256 reg_ptr = AllocTempRef(); 1257 if (range_check) { 1258 reg_max = AllocTemp(); 1259 Load32Disp(rl_obj.reg, count_offset, reg_max); 1260 MarkPossibleNullPointerException(info->opt_flags); 1261 } 1262 Load32Disp(rl_obj.reg, offset_offset, reg_off); 1263 MarkPossibleNullPointerException(info->opt_flags); 1264 LoadRefDisp(rl_obj.reg, value_offset, reg_ptr, kNotVolatile); 1265 if (range_check) { 1266 // Set up a slow path to allow retry in case of bounds violation */ 1267 OpRegReg(kOpCmp, rl_idx.reg, reg_max); 1268 FreeTemp(reg_max); 1269 range_check_branch = OpCondBranch(kCondUge, nullptr); 1270 } 1271 OpRegImm(kOpAdd, reg_ptr, data_offset); 1272 if (rl_idx.is_const) { 1273 OpRegImm(kOpAdd, reg_off, mir_graph_->ConstantValue(rl_idx.orig_sreg)); 1274 } else { 1275 OpRegReg(kOpAdd, reg_off, rl_idx.reg); 1276 } 1277 FreeTemp(rl_obj.reg); 1278 if (rl_idx.location == kLocPhysReg) { 1279 FreeTemp(rl_idx.reg); 1280 } 1281 RegLocation rl_dest = InlineTarget(info); 1282 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1283 LoadBaseIndexed(reg_ptr, reg_off, rl_result.reg, 1, kUnsignedHalf); 1284 FreeTemp(reg_off); 1285 FreeTemp(reg_ptr); 1286 StoreValue(rl_dest, rl_result); 1287 if (range_check) { 1288 DCHECK(range_check_branch != nullptr); 1289 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've already null checked. 1290 AddIntrinsicSlowPath(info, range_check_branch); 1291 } 1292 return true; 1293 } 1294 1295 // Generates an inlined String.is_empty or String.length. 1296 bool Mir2Lir::GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty) { 1297 if (cu_->instruction_set == kMips) { 1298 // TODO - add Mips implementation 1299 return false; 1300 } 1301 // dst = src.length(); 1302 RegLocation rl_obj = info->args[0]; 1303 rl_obj = LoadValue(rl_obj, kRefReg); 1304 RegLocation rl_dest = InlineTarget(info); 1305 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1306 GenNullCheck(rl_obj.reg, info->opt_flags); 1307 Load32Disp(rl_obj.reg, mirror::String::CountOffset().Int32Value(), rl_result.reg); 1308 MarkPossibleNullPointerException(info->opt_flags); 1309 if (is_empty) { 1310 // dst = (dst == 0); 1311 if (cu_->instruction_set == kThumb2) { 1312 RegStorage t_reg = AllocTemp(); 1313 OpRegReg(kOpNeg, t_reg, rl_result.reg); 1314 OpRegRegReg(kOpAdc, rl_result.reg, rl_result.reg, t_reg); 1315 } else if (cu_->instruction_set == kArm64) { 1316 OpRegImm(kOpSub, rl_result.reg, 1); 1317 OpRegRegImm(kOpLsr, rl_result.reg, rl_result.reg, 31); 1318 } else { 1319 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 1320 OpRegImm(kOpSub, rl_result.reg, 1); 1321 OpRegImm(kOpLsr, rl_result.reg, 31); 1322 } 1323 } 1324 StoreValue(rl_dest, rl_result); 1325 return true; 1326 } 1327 1328 bool Mir2Lir::GenInlinedReverseBytes(CallInfo* info, OpSize size) { 1329 if (cu_->instruction_set == kMips) { 1330 // TODO - add Mips implementation. 1331 return false; 1332 } 1333 RegLocation rl_src_i = info->args[0]; 1334 RegLocation rl_i = (size == k64) ? LoadValueWide(rl_src_i, kCoreReg) : LoadValue(rl_src_i, kCoreReg); 1335 RegLocation rl_dest = (size == k64) ? InlineTargetWide(info) : InlineTarget(info); // result reg 1336 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1337 if (size == k64) { 1338 if (cu_->instruction_set == kArm64 || cu_->instruction_set == kX86_64) { 1339 OpRegReg(kOpRev, rl_result.reg, rl_i.reg); 1340 StoreValueWide(rl_dest, rl_result); 1341 return true; 1342 } 1343 RegStorage r_i_low = rl_i.reg.GetLow(); 1344 if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { 1345 // First REV shall clobber rl_result.reg.GetReg(), save the value in a temp for the second REV. 1346 r_i_low = AllocTemp(); 1347 OpRegCopy(r_i_low, rl_i.reg); 1348 } 1349 OpRegReg(kOpRev, rl_result.reg.GetLow(), rl_i.reg.GetHigh()); 1350 OpRegReg(kOpRev, rl_result.reg.GetHigh(), r_i_low); 1351 if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { 1352 FreeTemp(r_i_low); 1353 } 1354 StoreValueWide(rl_dest, rl_result); 1355 } else { 1356 DCHECK(size == k32 || size == kSignedHalf); 1357 OpKind op = (size == k32) ? kOpRev : kOpRevsh; 1358 OpRegReg(op, rl_result.reg, rl_i.reg); 1359 StoreValue(rl_dest, rl_result); 1360 } 1361 return true; 1362 } 1363 1364 bool Mir2Lir::GenInlinedAbsInt(CallInfo* info) { 1365 if (cu_->instruction_set == kMips) { 1366 // TODO - add Mips implementation 1367 return false; 1368 } 1369 RegLocation rl_src = info->args[0]; 1370 rl_src = LoadValue(rl_src, kCoreReg); 1371 RegLocation rl_dest = InlineTarget(info); 1372 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1373 RegStorage sign_reg = AllocTemp(); 1374 // abs(x) = y<=x>>31, (x+y)^y. 1375 OpRegRegImm(kOpAsr, sign_reg, rl_src.reg, 31); 1376 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, sign_reg); 1377 OpRegReg(kOpXor, rl_result.reg, sign_reg); 1378 StoreValue(rl_dest, rl_result); 1379 return true; 1380 } 1381 1382 bool Mir2Lir::GenInlinedAbsLong(CallInfo* info) { 1383 if (cu_->instruction_set == kMips) { 1384 // TODO - add Mips implementation 1385 return false; 1386 } 1387 RegLocation rl_src = info->args[0]; 1388 rl_src = LoadValueWide(rl_src, kCoreReg); 1389 RegLocation rl_dest = InlineTargetWide(info); 1390 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1391 1392 // If on x86 or if we would clobber a register needed later, just copy the source first. 1393 if (cu_->instruction_set != kX86_64 && 1394 (cu_->instruction_set == kX86 || 1395 rl_result.reg.GetLowReg() == rl_src.reg.GetHighReg())) { 1396 OpRegCopyWide(rl_result.reg, rl_src.reg); 1397 if (rl_result.reg.GetLowReg() != rl_src.reg.GetLowReg() && 1398 rl_result.reg.GetLowReg() != rl_src.reg.GetHighReg() && 1399 rl_result.reg.GetHighReg() != rl_src.reg.GetLowReg() && 1400 rl_result.reg.GetHighReg() != rl_src.reg.GetHighReg()) { 1401 // Reuse source registers to avoid running out of temps. 1402 FreeTemp(rl_src.reg); 1403 } 1404 rl_src = rl_result; 1405 } 1406 1407 // abs(x) = y<=x>>31, (x+y)^y. 1408 RegStorage sign_reg; 1409 if (cu_->instruction_set == kX86_64) { 1410 sign_reg = AllocTempWide(); 1411 OpRegRegImm(kOpAsr, sign_reg, rl_src.reg, 63); 1412 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, sign_reg); 1413 OpRegReg(kOpXor, rl_result.reg, sign_reg); 1414 } else { 1415 sign_reg = AllocTemp(); 1416 OpRegRegImm(kOpAsr, sign_reg, rl_src.reg.GetHigh(), 31); 1417 OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src.reg.GetLow(), sign_reg); 1418 OpRegRegReg(kOpAdc, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), sign_reg); 1419 OpRegReg(kOpXor, rl_result.reg.GetLow(), sign_reg); 1420 OpRegReg(kOpXor, rl_result.reg.GetHigh(), sign_reg); 1421 } 1422 FreeTemp(sign_reg); 1423 StoreValueWide(rl_dest, rl_result); 1424 return true; 1425 } 1426 1427 bool Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) { 1428 // Currently implemented only for ARM64 1429 return false; 1430 } 1431 1432 bool Mir2Lir::GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) { 1433 // Currently implemented only for ARM64 1434 return false; 1435 } 1436 1437 bool Mir2Lir::GenInlinedCeil(CallInfo* info) { 1438 return false; 1439 } 1440 1441 bool Mir2Lir::GenInlinedFloor(CallInfo* info) { 1442 return false; 1443 } 1444 1445 bool Mir2Lir::GenInlinedRint(CallInfo* info) { 1446 return false; 1447 } 1448 1449 bool Mir2Lir::GenInlinedRound(CallInfo* info, bool is_double) { 1450 return false; 1451 } 1452 1453 bool Mir2Lir::GenInlinedFloatCvt(CallInfo* info) { 1454 if (cu_->instruction_set == kMips) { 1455 // TODO - add Mips implementation 1456 return false; 1457 } 1458 RegLocation rl_src = info->args[0]; 1459 RegLocation rl_dest = InlineTarget(info); 1460 StoreValue(rl_dest, rl_src); 1461 return true; 1462 } 1463 1464 bool Mir2Lir::GenInlinedDoubleCvt(CallInfo* info) { 1465 if (cu_->instruction_set == kMips) { 1466 // TODO - add Mips implementation 1467 return false; 1468 } 1469 RegLocation rl_src = info->args[0]; 1470 RegLocation rl_dest = InlineTargetWide(info); 1471 StoreValueWide(rl_dest, rl_src); 1472 return true; 1473 } 1474 1475 bool Mir2Lir::GenInlinedArrayCopyCharArray(CallInfo* info) { 1476 return false; 1477 } 1478 1479 1480 /* 1481 * Fast String.indexOf(I) & (II). Tests for simple case of char <= 0xFFFF, 1482 * otherwise bails to standard library code. 1483 */ 1484 bool Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 1485 if (cu_->instruction_set == kMips) { 1486 // TODO - add Mips implementation 1487 return false; 1488 } 1489 if (cu_->instruction_set == kX86_64) { 1490 // TODO - add kX86_64 implementation 1491 return false; 1492 } 1493 RegLocation rl_obj = info->args[0]; 1494 RegLocation rl_char = info->args[1]; 1495 if (rl_char.is_const && (mir_graph_->ConstantValue(rl_char) & ~0xFFFF) != 0) { 1496 // Code point beyond 0xFFFF. Punt to the real String.indexOf(). 1497 return false; 1498 } 1499 1500 ClobberCallerSave(); 1501 LockCallTemps(); // Using fixed registers 1502 RegStorage reg_ptr = TargetReg(kArg0, kRef); 1503 RegStorage reg_char = TargetReg(kArg1, kNotWide); 1504 RegStorage reg_start = TargetReg(kArg2, kNotWide); 1505 1506 LoadValueDirectFixed(rl_obj, reg_ptr); 1507 LoadValueDirectFixed(rl_char, reg_char); 1508 if (zero_based) { 1509 LoadConstant(reg_start, 0); 1510 } else { 1511 RegLocation rl_start = info->args[2]; // 3rd arg only present in III flavor of IndexOf. 1512 LoadValueDirectFixed(rl_start, reg_start); 1513 } 1514 RegStorage r_tgt = LoadHelper(kQuickIndexOf); 1515 GenExplicitNullCheck(reg_ptr, info->opt_flags); 1516 LIR* high_code_point_branch = 1517 rl_char.is_const ? nullptr : OpCmpImmBranch(kCondGt, reg_char, 0xFFFF, nullptr); 1518 // NOTE: not a safepoint 1519 OpReg(kOpBlx, r_tgt); 1520 if (!rl_char.is_const) { 1521 // Add the slow path for code points beyond 0xFFFF. 1522 DCHECK(high_code_point_branch != nullptr); 1523 LIR* resume_tgt = NewLIR0(kPseudoTargetLabel); 1524 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. 1525 AddIntrinsicSlowPath(info, high_code_point_branch, resume_tgt); 1526 ClobberCallerSave(); // We must clobber everything because slow path will return here 1527 } else { 1528 DCHECK_EQ(mir_graph_->ConstantValue(rl_char) & ~0xFFFF, 0); 1529 DCHECK(high_code_point_branch == nullptr); 1530 } 1531 RegLocation rl_return = GetReturn(kCoreReg); 1532 RegLocation rl_dest = InlineTarget(info); 1533 StoreValue(rl_dest, rl_return); 1534 return true; 1535 } 1536 1537 /* Fast string.compareTo(Ljava/lang/string;)I. */ 1538 bool Mir2Lir::GenInlinedStringCompareTo(CallInfo* info) { 1539 if (cu_->instruction_set == kMips) { 1540 // TODO - add Mips implementation 1541 return false; 1542 } 1543 ClobberCallerSave(); 1544 LockCallTemps(); // Using fixed registers 1545 RegStorage reg_this = TargetReg(kArg0, kRef); 1546 RegStorage reg_cmp = TargetReg(kArg1, kRef); 1547 1548 RegLocation rl_this = info->args[0]; 1549 RegLocation rl_cmp = info->args[1]; 1550 LoadValueDirectFixed(rl_this, reg_this); 1551 LoadValueDirectFixed(rl_cmp, reg_cmp); 1552 RegStorage r_tgt; 1553 if (cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64) { 1554 r_tgt = LoadHelper(kQuickStringCompareTo); 1555 } else { 1556 r_tgt = RegStorage::InvalidReg(); 1557 } 1558 GenExplicitNullCheck(reg_this, info->opt_flags); 1559 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. 1560 // TUNING: check if rl_cmp.s_reg_low is already null checked 1561 LIR* cmp_null_check_branch = OpCmpImmBranch(kCondEq, reg_cmp, 0, nullptr); 1562 AddIntrinsicSlowPath(info, cmp_null_check_branch); 1563 // NOTE: not a safepoint 1564 CallHelper(r_tgt, kQuickStringCompareTo, false, true); 1565 RegLocation rl_return = GetReturn(kCoreReg); 1566 RegLocation rl_dest = InlineTarget(info); 1567 StoreValue(rl_dest, rl_return); 1568 return true; 1569 } 1570 1571 bool Mir2Lir::GenInlinedCurrentThread(CallInfo* info) { 1572 RegLocation rl_dest = InlineTarget(info); 1573 1574 // Early exit if the result is unused. 1575 if (rl_dest.orig_sreg < 0) { 1576 return true; 1577 } 1578 1579 RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); 1580 1581 switch (cu_->instruction_set) { 1582 case kArm: 1583 // Fall-through. 1584 case kThumb2: 1585 // Fall-through. 1586 case kMips: 1587 Load32Disp(TargetPtrReg(kSelf), Thread::PeerOffset<4>().Int32Value(), rl_result.reg); 1588 break; 1589 1590 case kArm64: 1591 LoadRefDisp(TargetPtrReg(kSelf), Thread::PeerOffset<8>().Int32Value(), rl_result.reg, 1592 kNotVolatile); 1593 break; 1594 1595 default: 1596 LOG(FATAL) << "Unexpected isa " << cu_->instruction_set; 1597 } 1598 StoreValue(rl_dest, rl_result); 1599 return true; 1600 } 1601 1602 bool Mir2Lir::GenInlinedUnsafeGet(CallInfo* info, 1603 bool is_long, bool is_volatile) { 1604 if (cu_->instruction_set == kMips) { 1605 // TODO - add Mips implementation 1606 return false; 1607 } 1608 // Unused - RegLocation rl_src_unsafe = info->args[0]; 1609 RegLocation rl_src_obj = info->args[1]; // Object 1610 RegLocation rl_src_offset = info->args[2]; // long low 1611 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] 1612 RegLocation rl_dest = is_long ? InlineTargetWide(info) : InlineTarget(info); // result reg 1613 1614 RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); 1615 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); 1616 RegLocation rl_result = EvalLoc(rl_dest, LocToRegClass(rl_dest), true); 1617 if (is_long) { 1618 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64 1619 || cu_->instruction_set == kArm64) { 1620 LoadBaseIndexed(rl_object.reg, rl_offset.reg, rl_result.reg, 0, k64); 1621 } else { 1622 RegStorage rl_temp_offset = AllocTemp(); 1623 OpRegRegReg(kOpAdd, rl_temp_offset, rl_object.reg, rl_offset.reg); 1624 LoadBaseDisp(rl_temp_offset, 0, rl_result.reg, k64, kNotVolatile); 1625 FreeTemp(rl_temp_offset); 1626 } 1627 } else { 1628 if (rl_result.ref) { 1629 LoadRefIndexed(rl_object.reg, rl_offset.reg, rl_result.reg, 0); 1630 } else { 1631 LoadBaseIndexed(rl_object.reg, rl_offset.reg, rl_result.reg, 0, k32); 1632 } 1633 } 1634 1635 if (is_volatile) { 1636 GenMemBarrier(kLoadAny); 1637 } 1638 1639 if (is_long) { 1640 StoreValueWide(rl_dest, rl_result); 1641 } else { 1642 StoreValue(rl_dest, rl_result); 1643 } 1644 return true; 1645 } 1646 1647 bool Mir2Lir::GenInlinedUnsafePut(CallInfo* info, bool is_long, 1648 bool is_object, bool is_volatile, bool is_ordered) { 1649 if (cu_->instruction_set == kMips) { 1650 // TODO - add Mips implementation 1651 return false; 1652 } 1653 // Unused - RegLocation rl_src_unsafe = info->args[0]; 1654 RegLocation rl_src_obj = info->args[1]; // Object 1655 RegLocation rl_src_offset = info->args[2]; // long low 1656 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] 1657 RegLocation rl_src_value = info->args[4]; // value to store 1658 if (is_volatile || is_ordered) { 1659 GenMemBarrier(kAnyStore); 1660 } 1661 RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); 1662 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); 1663 RegLocation rl_value; 1664 if (is_long) { 1665 rl_value = LoadValueWide(rl_src_value, kCoreReg); 1666 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64 1667 || cu_->instruction_set == kArm64) { 1668 StoreBaseIndexed(rl_object.reg, rl_offset.reg, rl_value.reg, 0, k64); 1669 } else { 1670 RegStorage rl_temp_offset = AllocTemp(); 1671 OpRegRegReg(kOpAdd, rl_temp_offset, rl_object.reg, rl_offset.reg); 1672 StoreBaseDisp(rl_temp_offset, 0, rl_value.reg, k64, kNotVolatile); 1673 FreeTemp(rl_temp_offset); 1674 } 1675 } else { 1676 rl_value = LoadValue(rl_src_value); 1677 if (rl_value.ref) { 1678 StoreRefIndexed(rl_object.reg, rl_offset.reg, rl_value.reg, 0); 1679 } else { 1680 StoreBaseIndexed(rl_object.reg, rl_offset.reg, rl_value.reg, 0, k32); 1681 } 1682 } 1683 1684 // Free up the temp early, to ensure x86 doesn't run out of temporaries in MarkGCCard. 1685 FreeTemp(rl_offset.reg); 1686 1687 if (is_volatile) { 1688 // Prevent reordering with a subsequent volatile load. 1689 // May also be needed to address store atomicity issues. 1690 GenMemBarrier(kAnyAny); 1691 } 1692 if (is_object) { 1693 MarkGCCard(rl_value.reg, rl_object.reg); 1694 } 1695 return true; 1696 } 1697 1698 void Mir2Lir::GenInvoke(CallInfo* info) { 1699 if ((info->opt_flags & MIR_INLINED) != 0) { 1700 // Already inlined but we may still need the null check. 1701 if (info->type != kStatic && 1702 ((cu_->disable_opt & (1 << kNullCheckElimination)) != 0 || 1703 (info->opt_flags & MIR_IGNORE_NULL_CHECK) == 0)) { 1704 RegLocation rl_obj = LoadValue(info->args[0], kRefReg); 1705 GenNullCheck(rl_obj.reg); 1706 } 1707 return; 1708 } 1709 DCHECK(cu_->compiler_driver->GetMethodInlinerMap() != nullptr); 1710 if (cu_->compiler_driver->GetMethodInlinerMap()->GetMethodInliner(cu_->dex_file) 1711 ->GenIntrinsic(this, info)) { 1712 return; 1713 } 1714 GenInvokeNoInline(info); 1715 } 1716 1717 static LIR* GenInvokeNoInlineCall(Mir2Lir* mir_to_lir, InvokeType type) { 1718 QuickEntrypointEnum trampoline; 1719 switch (type) { 1720 case kInterface: 1721 trampoline = kQuickInvokeInterfaceTrampolineWithAccessCheck; 1722 break; 1723 case kDirect: 1724 trampoline = kQuickInvokeDirectTrampolineWithAccessCheck; 1725 break; 1726 case kStatic: 1727 trampoline = kQuickInvokeStaticTrampolineWithAccessCheck; 1728 break; 1729 case kSuper: 1730 trampoline = kQuickInvokeSuperTrampolineWithAccessCheck; 1731 break; 1732 case kVirtual: 1733 trampoline = kQuickInvokeVirtualTrampolineWithAccessCheck; 1734 break; 1735 default: 1736 LOG(FATAL) << "Unexpected invoke type"; 1737 trampoline = kQuickInvokeInterfaceTrampolineWithAccessCheck; 1738 } 1739 return mir_to_lir->InvokeTrampoline(kOpBlx, RegStorage::InvalidReg(), trampoline); 1740 } 1741 1742 void Mir2Lir::GenInvokeNoInline(CallInfo* info) { 1743 int call_state = 0; 1744 LIR* null_ck; 1745 LIR** p_null_ck = NULL; 1746 NextCallInsn next_call_insn; 1747 FlushAllRegs(); /* Everything to home location */ 1748 // Explicit register usage 1749 LockCallTemps(); 1750 1751 const MirMethodLoweringInfo& method_info = mir_graph_->GetMethodLoweringInfo(info->mir); 1752 cu_->compiler_driver->ProcessedInvoke(method_info.GetInvokeType(), method_info.StatsFlags()); 1753 BeginInvoke(info); 1754 InvokeType original_type = static_cast<InvokeType>(method_info.GetInvokeType()); 1755 info->type = static_cast<InvokeType>(method_info.GetSharpType()); 1756 bool fast_path = method_info.FastPath(); 1757 bool skip_this; 1758 if (info->type == kInterface) { 1759 next_call_insn = fast_path ? NextInterfaceCallInsn : NextInterfaceCallInsnWithAccessCheck; 1760 skip_this = fast_path; 1761 } else if (info->type == kDirect) { 1762 if (fast_path) { 1763 p_null_ck = &null_ck; 1764 } 1765 next_call_insn = fast_path ? NextSDCallInsn : NextDirectCallInsnSP; 1766 skip_this = false; 1767 } else if (info->type == kStatic) { 1768 next_call_insn = fast_path ? NextSDCallInsn : NextStaticCallInsnSP; 1769 skip_this = false; 1770 } else if (info->type == kSuper) { 1771 DCHECK(!fast_path); // Fast path is a direct call. 1772 next_call_insn = NextSuperCallInsnSP; 1773 skip_this = false; 1774 } else { 1775 DCHECK_EQ(info->type, kVirtual); 1776 next_call_insn = fast_path ? NextVCallInsn : NextVCallInsnSP; 1777 skip_this = fast_path; 1778 } 1779 MethodReference target_method = method_info.GetTargetMethod(); 1780 if (!info->is_range) { 1781 call_state = GenDalvikArgsNoRange(info, call_state, p_null_ck, 1782 next_call_insn, target_method, method_info.VTableIndex(), 1783 method_info.DirectCode(), method_info.DirectMethod(), 1784 original_type, skip_this); 1785 } else { 1786 call_state = GenDalvikArgsRange(info, call_state, p_null_ck, 1787 next_call_insn, target_method, method_info.VTableIndex(), 1788 method_info.DirectCode(), method_info.DirectMethod(), 1789 original_type, skip_this); 1790 } 1791 // Finish up any of the call sequence not interleaved in arg loading 1792 while (call_state >= 0) { 1793 call_state = next_call_insn(cu_, info, call_state, target_method, method_info.VTableIndex(), 1794 method_info.DirectCode(), method_info.DirectMethod(), original_type); 1795 } 1796 LIR* call_inst; 1797 if (cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64) { 1798 call_inst = OpReg(kOpBlx, TargetPtrReg(kInvokeTgt)); 1799 } else { 1800 if (fast_path) { 1801 if (method_info.DirectCode() == static_cast<uintptr_t>(-1)) { 1802 // We can have the linker fixup a call relative. 1803 call_inst = 1804 reinterpret_cast<X86Mir2Lir*>(this)->CallWithLinkerFixup(target_method, info->type); 1805 } else { 1806 int32_t offset = mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset( 1807 InstructionSetPointerSize(cu_->instruction_set)).Int32Value(); 1808 call_inst = OpMem(kOpBlx, TargetReg(kArg0, kRef), offset); 1809 } 1810 } else { 1811 call_inst = GenInvokeNoInlineCall(this, info->type); 1812 } 1813 } 1814 EndInvoke(info); 1815 MarkSafepointPC(call_inst); 1816 1817 FreeCallTemps(); 1818 if (info->result.location != kLocInvalid) { 1819 // We have a following MOVE_RESULT - do it now. 1820 if (info->result.wide) { 1821 RegLocation ret_loc = GetReturnWide(LocToRegClass(info->result)); 1822 StoreValueWide(info->result, ret_loc); 1823 } else { 1824 RegLocation ret_loc = GetReturn(LocToRegClass(info->result)); 1825 StoreValue(info->result, ret_loc); 1826 } 1827 } 1828 } 1829 1830 } // namespace art 1831
