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    Searched refs:MCPhysReg (Results 26 - 50 of 63) sorted by null

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  /external/llvm/lib/Target/Hexagon/
HexagonRegisterInfo.cpp 46 const MCPhysReg *
48 static const MCPhysReg CalleeSavedRegsV2[] = {
51 static const MCPhysReg CalleeSavedRegsV3[] = {
HexagonISelLowering.cpp 187 static const MCPhysReg RegList[] = {
210 static const MCPhysReg RegList1[] = {
213 static const MCPhysReg RegList2[] = {
    [all...]
HexagonVLIWPacketizer.cpp 395 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
    [all...]
  /external/llvm/lib/Target/XCore/
XCoreRegisterInfo.cpp 210 const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
214 static const MCPhysReg CalleeSavedRegs[] = {
219 static const MCPhysReg CalleeSavedRegsFP[] = {
  /external/llvm/lib/Target/ARM/
ARMBaseRegisterInfo.cpp 59 const MCPhysReg*
61 const MCPhysReg *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI())
218 ArrayRef<MCPhysReg> Order,
219 SmallVectorImpl<MCPhysReg> &Hints,
Thumb1FrameLowering.cpp 299 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
334 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs();
ARMFrameLowering.cpp 94 const MCPhysReg *CSRegs) {
599 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
    [all...]
  /external/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.cpp 25 const MCPhysReg *
SystemZFrameLowering.cpp 95 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
  /external/llvm/lib/Target/AArch64/
AArch64FrameLowering.cpp 406 static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs) {
413 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
496 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
    [all...]
AArch64RegisterInfo.cpp 40 const MCPhysReg *
AArch64ISelLowering.h 310 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.cpp 41 const MCPhysReg*
  /external/llvm/lib/CodeGen/
CriticalAntiDepBreaker.cpp 79 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
406 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
RegAllocFast.cpp 536 ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
539 for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
551 for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
    [all...]
RegisterScavenging.cpp 95 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
AggressiveAntiDepBreaker.cpp 173 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
613 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
    [all...]
RegAllocPBQP.cpp 219 ArrayRef<MCPhysReg> rawOrder = trc->getRawAllocationOrder(*mf);
MachineFunction.cpp 611 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); CSR && *CSR; ++CSR)
    [all...]
PrologEpilogInserter.cpp 247 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F);
    [all...]
  /external/llvm/lib/Target/Mips/
MipsISelLowering.h 391 const MCPhysReg *intArgRegs() const;
412 const MCPhysReg *shadowRegs() const;
MipsISelLowering.cpp 59 static const MCPhysReg O32IntRegs[4] = {
63 static const MCPhysReg Mips64IntRegs[8] = {
68 static const MCPhysReg Mips64DPRegs[8] = {
    [all...]
MipsDelaySlotFiller.cpp 318 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(); *R; ++R)
  /external/llvm/lib/Target/X86/
X86ISelLowering.h     [all...]
  /external/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp     [all...]

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12 3