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      1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the AArch64 implementation of the TargetRegisterInfo
     11 // class.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #include "AArch64RegisterInfo.h"
     16 #include "AArch64FrameLowering.h"
     17 #include "AArch64InstrInfo.h"
     18 #include "AArch64Subtarget.h"
     19 #include "MCTargetDesc/AArch64AddressingModes.h"
     20 #include "llvm/ADT/BitVector.h"
     21 #include "llvm/CodeGen/MachineFrameInfo.h"
     22 #include "llvm/CodeGen/MachineInstrBuilder.h"
     23 #include "llvm/CodeGen/MachineRegisterInfo.h"
     24 #include "llvm/CodeGen/RegisterScavenging.h"
     25 #include "llvm/IR/Function.h"
     26 #include "llvm/Support/CommandLine.h"
     27 #include "llvm/Support/raw_ostream.h"
     28 #include "llvm/Target/TargetFrameLowering.h"
     29 #include "llvm/Target/TargetOptions.h"
     30 
     31 using namespace llvm;
     32 
     33 #define GET_REGINFO_TARGET_DESC
     34 #include "AArch64GenRegisterInfo.inc"
     35 
     36 AArch64RegisterInfo::AArch64RegisterInfo(const AArch64InstrInfo *tii,
     37                                          const AArch64Subtarget *sti)
     38     : AArch64GenRegisterInfo(AArch64::LR), TII(tii), STI(sti) {}
     39 
     40 const MCPhysReg *
     41 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
     42   assert(MF && "Invalid MachineFunction pointer.");
     43   if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
     44     return CSR_AArch64_AllRegs_SaveList;
     45   else
     46     return CSR_AArch64_AAPCS_SaveList;
     47 }
     48 
     49 const uint32_t *
     50 AArch64RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
     51   if (CC == CallingConv::AnyReg)
     52     return CSR_AArch64_AllRegs_RegMask;
     53   else
     54     return CSR_AArch64_AAPCS_RegMask;
     55 }
     56 
     57 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
     58   if (STI->isTargetDarwin())
     59     return CSR_AArch64_TLS_Darwin_RegMask;
     60 
     61   assert(STI->isTargetELF() && "only expect Darwin or ELF TLS");
     62   return CSR_AArch64_TLS_ELF_RegMask;
     63 }
     64 
     65 const uint32_t *
     66 AArch64RegisterInfo::getThisReturnPreservedMask(CallingConv::ID) const {
     67   // This should return a register mask that is the same as that returned by
     68   // getCallPreservedMask but that additionally preserves the register used for
     69   // the first i64 argument (which must also be the register used to return a
     70   // single i64 return value)
     71   //
     72   // In case that the calling convention does not use the same register for
     73   // both, the function should return NULL (does not currently apply)
     74   return CSR_AArch64_AAPCS_ThisReturn_RegMask;
     75 }
     76 
     77 BitVector
     78 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     79   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
     80 
     81   // FIXME: avoid re-calculating this every time.
     82   BitVector Reserved(getNumRegs());
     83   Reserved.set(AArch64::SP);
     84   Reserved.set(AArch64::XZR);
     85   Reserved.set(AArch64::WSP);
     86   Reserved.set(AArch64::WZR);
     87 
     88   if (TFI->hasFP(MF) || STI->isTargetDarwin()) {
     89     Reserved.set(AArch64::FP);
     90     Reserved.set(AArch64::W29);
     91   }
     92 
     93   if (STI->isTargetDarwin()) {
     94     Reserved.set(AArch64::X18); // Platform register
     95     Reserved.set(AArch64::W18);
     96   }
     97 
     98   if (hasBasePointer(MF)) {
     99     Reserved.set(AArch64::X19);
    100     Reserved.set(AArch64::W19);
    101   }
    102 
    103   return Reserved;
    104 }
    105 
    106 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
    107                                       unsigned Reg) const {
    108   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    109 
    110   switch (Reg) {
    111   default:
    112     break;
    113   case AArch64::SP:
    114   case AArch64::XZR:
    115   case AArch64::WSP:
    116   case AArch64::WZR:
    117     return true;
    118   case AArch64::X18:
    119   case AArch64::W18:
    120     return STI->isTargetDarwin();
    121   case AArch64::FP:
    122   case AArch64::W29:
    123     return TFI->hasFP(MF) || STI->isTargetDarwin();
    124   case AArch64::W19:
    125   case AArch64::X19:
    126     return hasBasePointer(MF);
    127   }
    128 
    129   return false;
    130 }
    131 
    132 const TargetRegisterClass *
    133 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
    134                                       unsigned Kind) const {
    135   return &AArch64::GPR64RegClass;
    136 }
    137 
    138 const TargetRegisterClass *
    139 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
    140   if (RC == &AArch64::CCRRegClass)
    141     return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
    142   return RC;
    143 }
    144 
    145 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
    146 
    147 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
    148   const MachineFrameInfo *MFI = MF.getFrameInfo();
    149 
    150   // In the presence of variable sized objects, if the fixed stack size is
    151   // large enough that referencing from the FP won't result in things being
    152   // in range relatively often, we can use a base pointer to allow access
    153   // from the other direction like the SP normally works.
    154   if (MFI->hasVarSizedObjects()) {
    155     // Conservatively estimate whether the negative offset from the frame
    156     // pointer will be sufficient to reach. If a function has a smallish
    157     // frame, it's less likely to have lots of spills and callee saved
    158     // space, so it's all more likely to be within range of the frame pointer.
    159     // If it's wrong, we'll materialize the constant and still get to the
    160     // object; it's just suboptimal. Negative offsets use the unscaled
    161     // load/store instructions, which have a 9-bit signed immediate.
    162     if (MFI->getLocalFrameSize() < 256)
    163       return false;
    164     return true;
    165   }
    166 
    167   return false;
    168 }
    169 
    170 unsigned
    171 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
    172   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    173 
    174   return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
    175 }
    176 
    177 bool AArch64RegisterInfo::requiresRegisterScavenging(
    178     const MachineFunction &MF) const {
    179   return true;
    180 }
    181 
    182 bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
    183     const MachineFunction &MF) const {
    184   return true;
    185 }
    186 
    187 bool
    188 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
    189   const MachineFrameInfo *MFI = MF.getFrameInfo();
    190   // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
    191   // to the stack pointer, so only put the emergency spill slot next to the
    192   // FP when there's no better way to access it (SP or base pointer).
    193   return MFI->hasVarSizedObjects() && !hasBasePointer(MF);
    194 }
    195 
    196 bool AArch64RegisterInfo::requiresFrameIndexScavenging(
    197     const MachineFunction &MF) const {
    198   return true;
    199 }
    200 
    201 bool
    202 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
    203   const MachineFrameInfo *MFI = MF.getFrameInfo();
    204   // Only consider eliminating leaf frames.
    205   if (MFI->hasCalls() || (MF.getTarget().Options.DisableFramePointerElim(MF) &&
    206                           MFI->adjustsStack()))
    207     return true;
    208   return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
    209 }
    210 
    211 /// needsFrameBaseReg - Returns true if the instruction's frame index
    212 /// reference would be better served by a base register other than FP
    213 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
    214 /// references it should create new base registers for.
    215 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
    216                                             int64_t Offset) const {
    217   for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
    218     assert(i < MI->getNumOperands() &&
    219            "Instr doesn't have FrameIndex operand!");
    220 
    221   // It's the load/store FI references that cause issues, as it can be difficult
    222   // to materialize the offset if it won't fit in the literal field. Estimate
    223   // based on the size of the local frame and some conservative assumptions
    224   // about the rest of the stack frame (note, this is pre-regalloc, so
    225   // we don't know everything for certain yet) whether this offset is likely
    226   // to be out of range of the immediate. Return true if so.
    227 
    228   // We only generate virtual base registers for loads and stores, so
    229   // return false for everything else.
    230   if (!MI->mayLoad() && !MI->mayStore())
    231     return false;
    232 
    233   // Without a virtual base register, if the function has variable sized
    234   // objects, all fixed-size local references will be via the frame pointer,
    235   // Approximate the offset and see if it's legal for the instruction.
    236   // Note that the incoming offset is based on the SP value at function entry,
    237   // so it'll be negative.
    238   MachineFunction &MF = *MI->getParent()->getParent();
    239   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    240   MachineFrameInfo *MFI = MF.getFrameInfo();
    241 
    242   // Estimate an offset from the frame pointer.
    243   // Conservatively assume all GPR callee-saved registers get pushed.
    244   // FP, LR, X19-X28, D8-D15. 64-bits each.
    245   int64_t FPOffset = Offset - 16 * 20;
    246   // Estimate an offset from the stack pointer.
    247   // The incoming offset is relating to the SP at the start of the function,
    248   // but when we access the local it'll be relative to the SP after local
    249   // allocation, so adjust our SP-relative offset by that allocation size.
    250   Offset += MFI->getLocalFrameSize();
    251   // Assume that we'll have at least some spill slots allocated.
    252   // FIXME: This is a total SWAG number. We should run some statistics
    253   //        and pick a real one.
    254   Offset += 128; // 128 bytes of spill slots
    255 
    256   // If there is a frame pointer, try using it.
    257   // The FP is only available if there is no dynamic realignment. We
    258   // don't know for sure yet whether we'll need that, so we guess based
    259   // on whether there are any local variables that would trigger it.
    260   if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, FPOffset))
    261     return false;
    262 
    263   // If we can reference via the stack pointer or base pointer, try that.
    264   // FIXME: This (and the code that resolves the references) can be improved
    265   //        to only disallow SP relative references in the live range of
    266   //        the VLA(s). In practice, it's unclear how much difference that
    267   //        would make, but it may be worth doing.
    268   if (isFrameOffsetLegal(MI, Offset))
    269     return false;
    270 
    271   // The offset likely isn't legal; we want to allocate a virtual base register.
    272   return true;
    273 }
    274 
    275 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
    276                                              int64_t Offset) const {
    277   assert(Offset <= INT_MAX && "Offset too big to fit in int.");
    278   assert(MI && "Unable to get the legal offset for nil instruction.");
    279   int SaveOffset = Offset;
    280   return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
    281 }
    282 
    283 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
    284 /// at the beginning of the basic block.
    285 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
    286                                                        unsigned BaseReg,
    287                                                        int FrameIdx,
    288                                                        int64_t Offset) const {
    289   MachineBasicBlock::iterator Ins = MBB->begin();
    290   DebugLoc DL; // Defaults to "unknown"
    291   if (Ins != MBB->end())
    292     DL = Ins->getDebugLoc();
    293 
    294   const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
    295   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
    296   const MachineFunction &MF = *MBB->getParent();
    297   MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
    298   unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
    299 
    300   BuildMI(*MBB, Ins, DL, MCID, BaseReg)
    301       .addFrameIndex(FrameIdx)
    302       .addImm(Offset)
    303       .addImm(Shifter);
    304 }
    305 
    306 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
    307                                             int64_t Offset) const {
    308   int Off = Offset; // ARM doesn't need the general 64-bit offsets
    309   unsigned i = 0;
    310 
    311   while (!MI.getOperand(i).isFI()) {
    312     ++i;
    313     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
    314   }
    315   bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
    316   assert(Done && "Unable to resolve frame index!");
    317   (void)Done;
    318 }
    319 
    320 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
    321                                               int SPAdj, unsigned FIOperandNum,
    322                                               RegScavenger *RS) const {
    323   assert(SPAdj == 0 && "Unexpected");
    324 
    325   MachineInstr &MI = *II;
    326   MachineBasicBlock &MBB = *MI.getParent();
    327   MachineFunction &MF = *MBB.getParent();
    328   const AArch64FrameLowering *TFI = static_cast<const AArch64FrameLowering *>(
    329       MF.getTarget().getFrameLowering());
    330 
    331   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
    332   unsigned FrameReg;
    333   int Offset;
    334 
    335   // Special handling of dbg_value, stackmap and patchpoint instructions.
    336   if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
    337       MI.getOpcode() == TargetOpcode::PATCHPOINT) {
    338     Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
    339                                              /*PreferFP=*/true);
    340     Offset += MI.getOperand(FIOperandNum + 1).getImm();
    341     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
    342     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
    343     return;
    344   }
    345 
    346   // Modify MI as necessary to handle as much of 'Offset' as possible
    347   Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
    348   if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
    349     return;
    350 
    351   assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
    352          "Emergency spill slot is out of reach");
    353 
    354   // If we get here, the immediate doesn't fit into the instruction.  We folded
    355   // as much as possible above.  Handle the rest, providing a register that is
    356   // SP+LargeImm.
    357   unsigned ScratchReg =
    358       MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
    359   emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
    360   MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
    361 }
    362 
    363 namespace llvm {
    364 
    365 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
    366                                                   MachineFunction &MF) const {
    367   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    368 
    369   switch (RC->getID()) {
    370   default:
    371     return 0;
    372   case AArch64::GPR32RegClassID:
    373   case AArch64::GPR32spRegClassID:
    374   case AArch64::GPR32allRegClassID:
    375   case AArch64::GPR64spRegClassID:
    376   case AArch64::GPR64allRegClassID:
    377   case AArch64::GPR64RegClassID:
    378   case AArch64::GPR32commonRegClassID:
    379   case AArch64::GPR64commonRegClassID:
    380     return 32 - 1                                      // XZR/SP
    381            - (TFI->hasFP(MF) || STI->isTargetDarwin()) // FP
    382            - STI->isTargetDarwin() // X18 reserved as platform register
    383            - hasBasePointer(MF);   // X19
    384   case AArch64::FPR8RegClassID:
    385   case AArch64::FPR16RegClassID:
    386   case AArch64::FPR32RegClassID:
    387   case AArch64::FPR64RegClassID:
    388   case AArch64::FPR128RegClassID:
    389     return 32;
    390 
    391   case AArch64::DDRegClassID:
    392   case AArch64::DDDRegClassID:
    393   case AArch64::DDDDRegClassID:
    394   case AArch64::QQRegClassID:
    395   case AArch64::QQQRegClassID:
    396   case AArch64::QQQQRegClassID:
    397     return 32;
    398 
    399   case AArch64::FPR128_loRegClassID:
    400     return 16;
    401   }
    402 }
    403 
    404 } // namespace llvm
    405