1 //===-- SystemZMCCodeEmitter.cpp - Convert SystemZ code to machine code ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SystemZMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/SystemZMCTargetDesc.h" 15 #include "MCTargetDesc/SystemZMCFixups.h" 16 #include "llvm/MC/MCCodeEmitter.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 21 using namespace llvm; 22 23 #define DEBUG_TYPE "mccodeemitter" 24 25 namespace { 26 class SystemZMCCodeEmitter : public MCCodeEmitter { 27 const MCInstrInfo &MCII; 28 MCContext &Ctx; 29 30 public: 31 SystemZMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 32 : MCII(mcii), Ctx(ctx) { 33 } 34 35 ~SystemZMCCodeEmitter() {} 36 37 // OVerride MCCodeEmitter. 38 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 39 SmallVectorImpl<MCFixup> &Fixups, 40 const MCSubtargetInfo &STI) const override; 41 42 private: 43 // Automatically generated by TableGen. 44 uint64_t getBinaryCodeForInstr(const MCInst &MI, 45 SmallVectorImpl<MCFixup> &Fixups, 46 const MCSubtargetInfo &STI) const; 47 48 // Called by the TableGen code to get the binary encoding of operand 49 // MO in MI. Fixups is the list of fixups against MI. 50 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 51 SmallVectorImpl<MCFixup> &Fixups, 52 const MCSubtargetInfo &STI) const; 53 54 // Called by the TableGen code to get the binary encoding of an address. 55 // The index or length, if any, is encoded first, followed by the base, 56 // followed by the displacement. In a 20-bit displacement, 57 // the low 12 bits are encoded before the high 8 bits. 58 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, 59 SmallVectorImpl<MCFixup> &Fixups, 60 const MCSubtargetInfo &STI) const; 61 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, 62 SmallVectorImpl<MCFixup> &Fixups, 63 const MCSubtargetInfo &STI) const; 64 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, 65 SmallVectorImpl<MCFixup> &Fixups, 66 const MCSubtargetInfo &STI) const; 67 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, 68 SmallVectorImpl<MCFixup> &Fixups, 69 const MCSubtargetInfo &STI) const; 70 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, 71 SmallVectorImpl<MCFixup> &Fixups, 72 const MCSubtargetInfo &STI) const; 73 74 // Operand OpNum of MI needs a PC-relative fixup of kind Kind at 75 // Offset bytes from the start of MI. Add the fixup to Fixups 76 // and return the in-place addend, which since we're a RELA target 77 // is always 0. 78 uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum, 79 SmallVectorImpl<MCFixup> &Fixups, 80 unsigned Kind, int64_t Offset) const; 81 82 uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, 83 SmallVectorImpl<MCFixup> &Fixups, 84 const MCSubtargetInfo &STI) const { 85 return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2); 86 } 87 uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, 88 SmallVectorImpl<MCFixup> &Fixups, 89 const MCSubtargetInfo &STI) const { 90 return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2); 91 } 92 }; 93 } // end anonymous namespace 94 95 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII, 96 const MCRegisterInfo &MRI, 97 const MCSubtargetInfo &MCSTI, 98 MCContext &Ctx) { 99 return new SystemZMCCodeEmitter(MCII, Ctx); 100 } 101 102 void SystemZMCCodeEmitter:: 103 EncodeInstruction(const MCInst &MI, raw_ostream &OS, 104 SmallVectorImpl<MCFixup> &Fixups, 105 const MCSubtargetInfo &STI) const { 106 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 107 unsigned Size = MCII.get(MI.getOpcode()).getSize(); 108 // Big-endian insertion of Size bytes. 109 unsigned ShiftValue = (Size * 8) - 8; 110 for (unsigned I = 0; I != Size; ++I) { 111 OS << uint8_t(Bits >> ShiftValue); 112 ShiftValue -= 8; 113 } 114 } 115 116 uint64_t SystemZMCCodeEmitter:: 117 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 118 SmallVectorImpl<MCFixup> &Fixups, 119 const MCSubtargetInfo &STI) const { 120 if (MO.isReg()) 121 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 122 if (MO.isImm()) 123 return static_cast<uint64_t>(MO.getImm()); 124 llvm_unreachable("Unexpected operand type!"); 125 } 126 127 uint64_t SystemZMCCodeEmitter:: 128 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, 129 SmallVectorImpl<MCFixup> &Fixups, 130 const MCSubtargetInfo &STI) const { 131 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 132 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 133 assert(isUInt<4>(Base) && isUInt<12>(Disp)); 134 return (Base << 12) | Disp; 135 } 136 137 uint64_t SystemZMCCodeEmitter:: 138 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, 139 SmallVectorImpl<MCFixup> &Fixups, 140 const MCSubtargetInfo &STI) const { 141 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 142 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 143 assert(isUInt<4>(Base) && isInt<20>(Disp)); 144 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); 145 } 146 147 uint64_t SystemZMCCodeEmitter:: 148 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, 149 SmallVectorImpl<MCFixup> &Fixups, 150 const MCSubtargetInfo &STI) const { 151 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 152 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 153 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 154 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); 155 return (Index << 16) | (Base << 12) | Disp; 156 } 157 158 uint64_t SystemZMCCodeEmitter:: 159 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, 160 SmallVectorImpl<MCFixup> &Fixups, 161 const MCSubtargetInfo &STI) const { 162 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 163 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 164 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 165 assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index)); 166 return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8) 167 | ((Disp & 0xff000) >> 12); 168 } 169 170 uint64_t SystemZMCCodeEmitter:: 171 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, 172 SmallVectorImpl<MCFixup> &Fixups, 173 const MCSubtargetInfo &STI) const { 174 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 175 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 176 uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1; 177 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len)); 178 return (Len << 16) | (Base << 12) | Disp; 179 } 180 181 uint64_t 182 SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum, 183 SmallVectorImpl<MCFixup> &Fixups, 184 unsigned Kind, int64_t Offset) const { 185 const MCOperand &MO = MI.getOperand(OpNum); 186 const MCExpr *Expr; 187 if (MO.isImm()) 188 Expr = MCConstantExpr::Create(MO.getImm() + Offset, Ctx); 189 else { 190 Expr = MO.getExpr(); 191 if (Offset) { 192 // The operand value is relative to the start of MI, but the fixup 193 // is relative to the operand field itself, which is Offset bytes 194 // into MI. Add Offset to the relocation value to cancel out 195 // this difference. 196 const MCExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx); 197 Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx); 198 } 199 } 200 Fixups.push_back(MCFixup::Create(Offset, Expr, (MCFixupKind)Kind)); 201 return 0; 202 } 203 204 #include "SystemZGenMCCodeEmitter.inc" 205
