| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 22 namespace ARM_AM {
25 default: return ARM_AM::no_shift;
26 case ISD::SHL: return ARM_AM::lsl;
27 case ISD::SRL: return ARM_AM::lsr;
28 case ISD::SRA: return ARM_AM::asr;
29 case ISD::ROTR: return ARM_AM::ror;
33 //case ARMISD::RRX: return ARM_AM::rrx;
36 } // end namespace ARM_AM
|
| ARMLoadStoreOptimizer.cpp | 147 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
154 case ARM_AM::ia: return ARM::LDMIA;
155 case ARM_AM::da: return ARM::LDMDA;
156 case ARM_AM::db: return ARM::LDMDB;
157 case ARM_AM::ib: return ARM::LDMIB;
163 case ARM_AM::ia: return ARM::STMIA;
164 case ARM_AM::da: return ARM::STMDA;
165 case ARM_AM::db: return ARM::STMDB;
166 case ARM_AM::ib: return ARM::STMIB;
174 case ARM_AM::ia: return ARM::tLDMIA
[all...] |
| ARMCodeEmitter.cpp | 405 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
407 case ARM_AM::asr: return 2;
408 case ARM_AM::lsl: return 0;
409 case ARM_AM::lsr: return 1;
410 case ARM_AM::ror:
411 case ARM_AM::rrx: return 3;
724 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
726 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
727 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
[all...] |
| ARMISelDAGToDAG.cpp | 95 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
190 return ARM_AM::getSOImmVal(Imm) != -1;
194 return ARM_AM::getSOImmVal(~Imm) != -1;
198 return ARM_AM::getT2SOImmVal(Imm) != -1;
202 return ARM_AM::getT2SOImmVal(~Imm) != -1;
456 ARM_AM::ShiftOpc ShOpcVal,
463 return ShOpcVal == ARM_AM::lsl &&
474 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
478 if (ShOpcVal == ARM_AM::no_shift) return false
[all...] |
| Thumb2InstrInfo.cpp | 231 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
291 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
296 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
298 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
304 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
313 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
315 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
476 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
502 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
507 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &
[all...] |
| ARMBaseInstrInfo.cpp | 170 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
171 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
173 if (ARM_AM::getSOImmVal(Amt) == -1)
182 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
183 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
196 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
197 unsigned Amt = ARM_AM::getAM3Offset(OffImm)
[all...] |
| ARMBaseRegisterInfo.cpp | 460 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
461 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
468 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
469 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
475 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
476 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
| ARMFastISel.cpp | 165 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
478 Imm = ARM_AM::getFP64Imm(Val);
481 Imm = ARM_AM::getFP32Imm(Val);
533 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
534 (ARM_AM::getSOImmVal(Imm) != -1);
[all...] |
| ARMTargetTransformInfo.cpp | 162 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
163 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
169 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
170 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
177 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
|
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| ARMFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 25 /// ARM_AM - ARM Addressing Mode Stuff
26 namespace ARM_AM {
48 case ARM_AM::asr: return "asr";
49 case ARM_AM::lsl: return "lsl";
50 case ARM_AM::lsr: return "lsr";
51 case ARM_AM::ror: return "ror";
52 case ARM_AM::rrx: return "rrx";
59 case ARM_AM::asr: return 2;
60 case ARM_AM::lsl: return 0;
61 case ARM_AM::lsr: return 1
[all...] |
| ARMMCCodeEmitter.cpp | 194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
197 case ARM_AM::da: return 0;
198 case ARM_AM::ia: return 1;
199 case ARM_AM::db: return 2;
200 case ARM_AM::ib: return 3;
205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
207 case ARM_AM::no_shift:
208 case ARM_AM::lsl: return 0;
209 case ARM_AM::lsr: return 1
[all...] |
| ARMAsmBackend.cpp | 412 if (Ctx && ARM_AM::getSOImmVal(Value) == -1)
415 return ARM_AM::getSOImmVal(Value) | (opc << 21);
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 42 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
44 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
48 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
51 if (ShOpc != ARM_AM::rrx) {
117 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
128 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
139 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 199 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
470 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
480 ARM_AM::ShiftOpc ShiftTy;
490 ARM_AM::ShiftOpc ShiftTy;
497 ARM_AM::ShiftOpc ShiftTy;
744 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
