1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMMCTargetDesc.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMFixupKinds.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/MC/MCAsmBackend.h" 16 #include "llvm/MC/MCAssembler.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDirectives.h" 19 #include "llvm/MC/MCELFObjectWriter.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCFixupKindInfo.h" 22 #include "llvm/MC/MCMachObjectWriter.h" 23 #include "llvm/MC/MCObjectWriter.h" 24 #include "llvm/MC/MCSectionELF.h" 25 #include "llvm/MC/MCSectionMachO.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/MC/MCValue.h" 28 #include "llvm/Support/ELF.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/MachO.h" 31 #include "llvm/Support/raw_ostream.h" 32 using namespace llvm; 33 34 namespace { 35 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 36 public: 37 ARMELFObjectWriter(uint8_t OSABI) 38 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 39 /*HasRelocationAddend*/ false) {} 40 }; 41 42 class ARMAsmBackend : public MCAsmBackend { 43 const MCSubtargetInfo* STI; 44 bool isThumbMode; // Currently emitting Thumb code. 45 bool IsLittleEndian; // Big or little endian. 46 public: 47 ARMAsmBackend(const Target &T, const StringRef TT, bool IsLittle) 48 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), 49 isThumbMode(TT.startswith("thumb")), IsLittleEndian(IsLittle) {} 50 51 ~ARMAsmBackend() { 52 delete STI; 53 } 54 55 unsigned getNumFixupKinds() const override { 56 return ARM::NumTargetFixupKinds; 57 } 58 59 bool hasNOP() const { 60 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; 61 } 62 63 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 64 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { 65 // This table *must* be in the order that the fixup_* kinds are defined in 66 // ARMFixupKinds.h. 67 // 68 // Name Offset (bits) Size (bits) Flags 69 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 70 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 71 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 72 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 73 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 74 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 75 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 76 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel | 77 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 78 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 79 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 80 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 81 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 82 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 83 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 84 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 85 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 86 { "fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 87 { "fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 88 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 89 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 90 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 91 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 92 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel | 93 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 94 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 95 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. 96 { "fixup_arm_movt_hi16", 0, 20, 0 }, 97 { "fixup_arm_movw_lo16", 0, 20, 0 }, 98 { "fixup_t2_movt_hi16", 0, 20, 0 }, 99 { "fixup_t2_movw_lo16", 0, 20, 0 }, 100 }; 101 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { 102 // This table *must* be in the order that the fixup_* kinds are defined in 103 // ARMFixupKinds.h. 104 // 105 // Name Offset (bits) Size (bits) Flags 106 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 107 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 108 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 109 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 110 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 111 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 112 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 113 { "fixup_thumb_adr_pcrel_10",8, 8, MCFixupKindInfo::FKF_IsPCRel | 114 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 115 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 116 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 117 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 118 { "fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel }, 119 { "fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel }, 120 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 121 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 122 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 123 { "fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel }, 124 { "fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel }, 125 { "fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel }, 126 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 127 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 128 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 129 { "fixup_arm_thumb_cp", 8, 8, MCFixupKindInfo::FKF_IsPCRel | 130 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 131 { "fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel }, 132 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. 133 { "fixup_arm_movt_hi16", 12, 20, 0 }, 134 { "fixup_arm_movw_lo16", 12, 20, 0 }, 135 { "fixup_t2_movt_hi16", 12, 20, 0 }, 136 { "fixup_t2_movw_lo16", 12, 20, 0 }, 137 }; 138 139 if (Kind < FirstTargetFixupKind) 140 return MCAsmBackend::getFixupKindInfo(Kind); 141 142 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 143 "Invalid kind!"); 144 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind]; 145 } 146 147 /// processFixupValue - Target hook to process the literal value of a fixup 148 /// if necessary. 149 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, 150 const MCFixup &Fixup, const MCFragment *DF, 151 const MCValue &Target, uint64_t &Value, 152 bool &IsResolved) override; 153 154 155 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 156 uint64_t Value, bool IsPCRel) const override; 157 158 bool mayNeedRelaxation(const MCInst &Inst) const override; 159 160 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 161 const MCRelaxableFragment *DF, 162 const MCAsmLayout &Layout) const override; 163 164 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override; 165 166 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; 167 168 void handleAssemblerFlag(MCAssemblerFlag Flag) override { 169 switch (Flag) { 170 default: break; 171 case MCAF_Code16: 172 setIsThumb(true); 173 break; 174 case MCAF_Code32: 175 setIsThumb(false); 176 break; 177 } 178 } 179 180 unsigned getPointerSize() const { return 4; } 181 bool isThumb() const { return isThumbMode; } 182 void setIsThumb(bool it) { isThumbMode = it; } 183 bool isLittle() const { return IsLittleEndian; } 184 }; 185 } // end anonymous namespace 186 187 static unsigned getRelaxedOpcode(unsigned Op) { 188 switch (Op) { 189 default: return Op; 190 case ARM::tBcc: return ARM::t2Bcc; 191 case ARM::tLDRpci: return ARM::t2LDRpci; 192 case ARM::tADR: return ARM::t2ADR; 193 case ARM::tB: return ARM::t2B; 194 case ARM::tCBZ: return ARM::tHINT; 195 case ARM::tCBNZ: return ARM::tHINT; 196 } 197 } 198 199 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 200 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 201 return true; 202 return false; 203 } 204 205 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 206 uint64_t Value, 207 const MCRelaxableFragment *DF, 208 const MCAsmLayout &Layout) const { 209 switch ((unsigned)Fixup.getKind()) { 210 case ARM::fixup_arm_thumb_br: { 211 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the 212 // low bit being an implied zero. There's an implied +4 offset for the 213 // branch, so we adjust the other way here to determine what's 214 // encodable. 215 // 216 // Relax if the value is too big for a (signed) i8. 217 int64_t Offset = int64_t(Value) - 4; 218 return Offset > 2046 || Offset < -2048; 219 } 220 case ARM::fixup_arm_thumb_bcc: { 221 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 222 // low bit being an implied zero. There's an implied +4 offset for the 223 // branch, so we adjust the other way here to determine what's 224 // encodable. 225 // 226 // Relax if the value is too big for a (signed) i8. 227 int64_t Offset = int64_t(Value) - 4; 228 return Offset > 254 || Offset < -256; 229 } 230 case ARM::fixup_thumb_adr_pcrel_10: 231 case ARM::fixup_arm_thumb_cp: { 232 // If the immediate is negative, greater than 1020, or not a multiple 233 // of four, the wide version of the instruction must be used. 234 int64_t Offset = int64_t(Value) - 4; 235 return Offset > 1020 || Offset < 0 || Offset & 3; 236 } 237 case ARM::fixup_arm_thumb_cb: 238 // If we have a Thumb CBZ or CBNZ instruction and its target is the next 239 // instruction it is is actually out of range for the instruction. 240 // It will be changed to a NOP. 241 int64_t Offset = (Value & ~1); 242 return Offset == 2; 243 } 244 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!"); 245 } 246 247 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 248 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 249 250 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 251 if (RelaxedOp == Inst.getOpcode()) { 252 SmallString<256> Tmp; 253 raw_svector_ostream OS(Tmp); 254 Inst.dump_pretty(OS); 255 OS << "\n"; 256 report_fatal_error("unexpected instruction to relax: " + OS.str()); 257 } 258 259 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we 260 // have to change the operands too. 261 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && 262 RelaxedOp == ARM::tHINT) { 263 Res.setOpcode(RelaxedOp); 264 Res.addOperand(MCOperand::CreateImm(0)); 265 Res.addOperand(MCOperand::CreateImm(14)); 266 Res.addOperand(MCOperand::CreateReg(0)); 267 return; 268 } 269 270 // The rest of instructions we're relaxing have the same operands. 271 // We just need to update to the proper opcode. 272 Res = Inst; 273 Res.setOpcode(RelaxedOp); 274 } 275 276 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 277 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 278 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 279 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0 280 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 281 if (isThumb()) { 282 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding 283 : Thumb1_16bitNopEncoding; 284 uint64_t NumNops = Count / 2; 285 for (uint64_t i = 0; i != NumNops; ++i) 286 OW->Write16(nopEncoding); 287 if (Count & 1) 288 OW->Write8(0); 289 return true; 290 } 291 // ARM mode 292 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding 293 : ARMv4_NopEncoding; 294 uint64_t NumNops = Count / 4; 295 for (uint64_t i = 0; i != NumNops; ++i) 296 OW->Write32(nopEncoding); 297 // FIXME: should this function return false when unable to write exactly 298 // 'Count' bytes with NOP encodings? 299 switch (Count % 4) { 300 default: break; // No leftover bytes to write 301 case 1: OW->Write8(0); break; 302 case 2: OW->Write16(0); break; 303 case 3: OW->Write16(0); OW->Write8(0xa0); break; 304 } 305 306 return true; 307 } 308 309 static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) { 310 if (IsLittleEndian) { 311 // Note that the halfwords are stored high first and low second in thumb; 312 // so we need to swap the fixup value here to map properly. 313 uint32_t Swapped = (Value & 0xFFFF0000) >> 16; 314 Swapped |= (Value & 0x0000FFFF) << 16; 315 return Swapped; 316 } 317 else 318 return Value; 319 } 320 321 static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, 322 bool IsLittleEndian) { 323 uint32_t Value; 324 325 if (IsLittleEndian) { 326 Value = (SecondHalf & 0xFFFF) << 16; 327 Value |= (FirstHalf & 0xFFFF); 328 } else { 329 Value = (SecondHalf & 0xFFFF); 330 Value |= (FirstHalf & 0xFFFF) << 16; 331 } 332 333 return Value; 334 } 335 336 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 337 bool IsPCRel, MCContext *Ctx, 338 bool IsLittleEndian) { 339 unsigned Kind = Fixup.getKind(); 340 switch (Kind) { 341 default: 342 llvm_unreachable("Unknown fixup kind!"); 343 case FK_Data_1: 344 case FK_Data_2: 345 case FK_Data_4: 346 return Value; 347 case FK_SecRel_2: 348 return Value; 349 case FK_SecRel_4: 350 return Value; 351 case ARM::fixup_arm_movt_hi16: 352 if (!IsPCRel) 353 Value >>= 16; 354 // Fallthrough 355 case ARM::fixup_arm_movw_lo16: { 356 unsigned Hi4 = (Value & 0xF000) >> 12; 357 unsigned Lo12 = Value & 0x0FFF; 358 // inst{19-16} = Hi4; 359 // inst{11-0} = Lo12; 360 Value = (Hi4 << 16) | (Lo12); 361 return Value; 362 } 363 case ARM::fixup_t2_movt_hi16: 364 if (!IsPCRel) 365 Value >>= 16; 366 // Fallthrough 367 case ARM::fixup_t2_movw_lo16: { 368 unsigned Hi4 = (Value & 0xF000) >> 12; 369 unsigned i = (Value & 0x800) >> 11; 370 unsigned Mid3 = (Value & 0x700) >> 8; 371 unsigned Lo8 = Value & 0x0FF; 372 // inst{19-16} = Hi4; 373 // inst{26} = i; 374 // inst{14-12} = Mid3; 375 // inst{7-0} = Lo8; 376 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 377 return swapHalfWords(Value, IsLittleEndian); 378 } 379 case ARM::fixup_arm_ldst_pcrel_12: 380 // ARM PC-relative values are offset by 8. 381 Value -= 4; 382 // FALLTHROUGH 383 case ARM::fixup_t2_ldst_pcrel_12: { 384 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 385 Value -= 4; 386 bool isAdd = true; 387 if ((int64_t)Value < 0) { 388 Value = -Value; 389 isAdd = false; 390 } 391 if (Ctx && Value >= 4096) 392 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 393 Value |= isAdd << 23; 394 395 // Same addressing mode as fixup_arm_pcrel_10, 396 // but with 16-bit halfwords swapped. 397 if (Kind == ARM::fixup_t2_ldst_pcrel_12) 398 return swapHalfWords(Value, IsLittleEndian); 399 400 return Value; 401 } 402 case ARM::fixup_thumb_adr_pcrel_10: 403 return ((Value - 4) >> 2) & 0xff; 404 case ARM::fixup_arm_adr_pcrel_12: { 405 // ARM PC-relative values are offset by 8. 406 Value -= 8; 407 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 408 if ((int64_t)Value < 0) { 409 Value = -Value; 410 opc = 2; // 0b0010 411 } 412 if (Ctx && ARM_AM::getSOImmVal(Value) == -1) 413 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 414 // Encode the immediate and shift the opcode into place. 415 return ARM_AM::getSOImmVal(Value) | (opc << 21); 416 } 417 418 case ARM::fixup_t2_adr_pcrel_12: { 419 Value -= 4; 420 unsigned opc = 0; 421 if ((int64_t)Value < 0) { 422 Value = -Value; 423 opc = 5; 424 } 425 426 uint32_t out = (opc << 21); 427 out |= (Value & 0x800) << 15; 428 out |= (Value & 0x700) << 4; 429 out |= (Value & 0x0FF); 430 431 return swapHalfWords(out, IsLittleEndian); 432 } 433 434 case ARM::fixup_arm_condbranch: 435 case ARM::fixup_arm_uncondbranch: 436 case ARM::fixup_arm_uncondbl: 437 case ARM::fixup_arm_condbl: 438 case ARM::fixup_arm_blx: 439 // These values don't encode the low two bits since they're always zero. 440 // Offset by 8 just as above. 441 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 442 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL) 443 return 0; 444 return 0xffffff & ((Value - 8) >> 2); 445 case ARM::fixup_t2_uncondbranch: { 446 Value = Value - 4; 447 Value >>= 1; // Low bit is not encoded. 448 449 uint32_t out = 0; 450 bool I = Value & 0x800000; 451 bool J1 = Value & 0x400000; 452 bool J2 = Value & 0x200000; 453 J1 ^= I; 454 J2 ^= I; 455 456 out |= I << 26; // S bit 457 out |= !J1 << 13; // J1 bit 458 out |= !J2 << 11; // J2 bit 459 out |= (Value & 0x1FF800) << 5; // imm6 field 460 out |= (Value & 0x0007FF); // imm11 field 461 462 return swapHalfWords(out, IsLittleEndian); 463 } 464 case ARM::fixup_t2_condbranch: { 465 Value = Value - 4; 466 Value >>= 1; // Low bit is not encoded. 467 468 uint64_t out = 0; 469 out |= (Value & 0x80000) << 7; // S bit 470 out |= (Value & 0x40000) >> 7; // J2 bit 471 out |= (Value & 0x20000) >> 4; // J1 bit 472 out |= (Value & 0x1F800) << 5; // imm6 field 473 out |= (Value & 0x007FF); // imm11 field 474 475 return swapHalfWords(out, IsLittleEndian); 476 } 477 case ARM::fixup_arm_thumb_bl: { 478 // The value doesn't encode the low bit (always zero) and is offset by 479 // four. The 32-bit immediate value is encoded as 480 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0) 481 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 482 // The value is encoded into disjoint bit positions in the destination 483 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 484 // J = either J1 or J2 bit 485 // 486 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII 487 // 488 // Note that the halfwords are stored high first, low second; so we need 489 // to transpose the fixup value here to map properly. 490 uint32_t offset = (Value - 4) >> 1; 491 uint32_t signBit = (offset & 0x800000) >> 23; 492 uint32_t I1Bit = (offset & 0x400000) >> 22; 493 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 494 uint32_t I2Bit = (offset & 0x200000) >> 21; 495 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 496 uint32_t imm10Bits = (offset & 0x1FF800) >> 11; 497 uint32_t imm11Bits = (offset & 0x000007FF); 498 499 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits); 500 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 501 (uint16_t)imm11Bits); 502 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 503 } 504 case ARM::fixup_arm_thumb_blx: { 505 // The value doesn't encode the low two bits (always zero) and is offset by 506 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as 507 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00) 508 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 509 // The value is encoded into disjoint bit positions in the destination 510 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 511 // J = either J1 or J2 bit, 0 = zero. 512 // 513 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0 514 // 515 // Note that the halfwords are stored high first, low second; so we need 516 // to transpose the fixup value here to map properly. 517 uint32_t offset = (Value - 2) >> 2; 518 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 519 if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_TLSCALL) 520 offset = 0; 521 uint32_t signBit = (offset & 0x400000) >> 22; 522 uint32_t I1Bit = (offset & 0x200000) >> 21; 523 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 524 uint32_t I2Bit = (offset & 0x100000) >> 20; 525 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 526 uint32_t imm10HBits = (offset & 0xFFC00) >> 10; 527 uint32_t imm10LBits = (offset & 0x3FF); 528 529 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits); 530 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 531 ((uint16_t)imm10LBits) << 1); 532 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian); 533 } 534 case ARM::fixup_arm_thumb_cp: 535 // Offset by 4, and don't encode the low two bits. Two bytes of that 536 // 'off by 4' is implicitly handled by the half-word ordering of the 537 // Thumb encoding, so we only need to adjust by 2 here. 538 return ((Value - 2) >> 2) & 0xff; 539 case ARM::fixup_arm_thumb_cb: { 540 // Offset by 4 and don't encode the lower bit, which is always 0. 541 uint32_t Binary = (Value - 4) >> 1; 542 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 543 } 544 case ARM::fixup_arm_thumb_br: 545 // Offset by 4 and don't encode the lower bit, which is always 0. 546 return ((Value - 4) >> 1) & 0x7ff; 547 case ARM::fixup_arm_thumb_bcc: 548 // Offset by 4 and don't encode the lower bit, which is always 0. 549 return ((Value - 4) >> 1) & 0xff; 550 case ARM::fixup_arm_pcrel_10_unscaled: { 551 Value = Value - 8; // ARM fixups offset by an additional word and don't 552 // need to adjust for the half-word ordering. 553 bool isAdd = true; 554 if ((int64_t)Value < 0) { 555 Value = -Value; 556 isAdd = false; 557 } 558 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8]. 559 if (Ctx && Value >= 256) 560 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 561 Value = (Value & 0xf) | ((Value & 0xf0) << 4); 562 return Value | (isAdd << 23); 563 } 564 case ARM::fixup_arm_pcrel_10: 565 Value = Value - 4; // ARM fixups offset by an additional word and don't 566 // need to adjust for the half-word ordering. 567 // Fall through. 568 case ARM::fixup_t2_pcrel_10: { 569 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 570 Value = Value - 4; 571 bool isAdd = true; 572 if ((int64_t)Value < 0) { 573 Value = -Value; 574 isAdd = false; 575 } 576 // These values don't encode the low two bits since they're always zero. 577 Value >>= 2; 578 if (Ctx && Value >= 256) 579 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value"); 580 Value |= isAdd << 23; 581 582 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 583 // swapped. 584 if (Kind == ARM::fixup_t2_pcrel_10) 585 return swapHalfWords(Value, IsLittleEndian); 586 587 return Value; 588 } 589 } 590 } 591 592 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm, 593 const MCAsmLayout &Layout, 594 const MCFixup &Fixup, 595 const MCFragment *DF, 596 const MCValue &Target, uint64_t &Value, 597 bool &IsResolved) { 598 const MCSymbolRefExpr *A = Target.getSymA(); 599 // Some fixups to thumb function symbols need the low bit (thumb bit) 600 // twiddled. 601 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 602 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 603 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 && 604 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 && 605 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 && 606 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 607 if (A) { 608 const MCSymbol &Sym = A->getSymbol().AliasedSymbol(); 609 if (Asm.isThumbFunc(&Sym)) 610 Value |= 1; 611 } 612 } 613 // For Thumb1 BL instruction, it is possible to be a long jump between 614 // the basic blocks of the same function. Thus, we would like to resolve 615 // the offset when the destination has the same MCFragment. 616 if (A && (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) { 617 const MCSymbol &Sym = A->getSymbol().AliasedSymbol(); 618 const MCSymbolData &SymData = Asm.getSymbolData(Sym); 619 IsResolved = (SymData.getFragment() == DF); 620 } 621 // We must always generate a relocation for BL/BLX instructions if we have 622 // a symbol to reference, as the linker relies on knowing the destination 623 // symbol's thumb-ness to get interworking right. 624 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx || 625 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx || 626 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl || 627 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl)) 628 IsResolved = false; 629 630 // Try to get the encoded value for the fixup as-if we're mapping it into 631 // the instruction. This allows adjustFixupValue() to issue a diagnostic 632 // if the value aren't invalid. 633 (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(), 634 IsLittleEndian); 635 } 636 637 /// getFixupKindNumBytes - The number of bytes the fixup may change. 638 static unsigned getFixupKindNumBytes(unsigned Kind) { 639 switch (Kind) { 640 default: 641 llvm_unreachable("Unknown fixup kind!"); 642 643 case FK_Data_1: 644 case ARM::fixup_arm_thumb_bcc: 645 case ARM::fixup_arm_thumb_cp: 646 case ARM::fixup_thumb_adr_pcrel_10: 647 return 1; 648 649 case FK_Data_2: 650 case ARM::fixup_arm_thumb_br: 651 case ARM::fixup_arm_thumb_cb: 652 return 2; 653 654 case ARM::fixup_arm_pcrel_10_unscaled: 655 case ARM::fixup_arm_ldst_pcrel_12: 656 case ARM::fixup_arm_pcrel_10: 657 case ARM::fixup_arm_adr_pcrel_12: 658 case ARM::fixup_arm_uncondbl: 659 case ARM::fixup_arm_condbl: 660 case ARM::fixup_arm_blx: 661 case ARM::fixup_arm_condbranch: 662 case ARM::fixup_arm_uncondbranch: 663 return 3; 664 665 case FK_Data_4: 666 case ARM::fixup_t2_ldst_pcrel_12: 667 case ARM::fixup_t2_condbranch: 668 case ARM::fixup_t2_uncondbranch: 669 case ARM::fixup_t2_pcrel_10: 670 case ARM::fixup_t2_adr_pcrel_12: 671 case ARM::fixup_arm_thumb_bl: 672 case ARM::fixup_arm_thumb_blx: 673 case ARM::fixup_arm_movt_hi16: 674 case ARM::fixup_arm_movw_lo16: 675 case ARM::fixup_t2_movt_hi16: 676 case ARM::fixup_t2_movw_lo16: 677 return 4; 678 679 case FK_SecRel_2: 680 return 2; 681 case FK_SecRel_4: 682 return 4; 683 } 684 } 685 686 /// getFixupKindContainerSizeBytes - The number of bytes of the 687 /// container involved in big endian. 688 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) { 689 switch (Kind) { 690 default: 691 llvm_unreachable("Unknown fixup kind!"); 692 693 case FK_Data_1: 694 return 1; 695 case FK_Data_2: 696 return 2; 697 case FK_Data_4: 698 return 4; 699 700 case ARM::fixup_arm_thumb_bcc: 701 case ARM::fixup_arm_thumb_cp: 702 case ARM::fixup_thumb_adr_pcrel_10: 703 case ARM::fixup_arm_thumb_br: 704 case ARM::fixup_arm_thumb_cb: 705 // Instruction size is 2 bytes. 706 return 2; 707 708 case ARM::fixup_arm_pcrel_10_unscaled: 709 case ARM::fixup_arm_ldst_pcrel_12: 710 case ARM::fixup_arm_pcrel_10: 711 case ARM::fixup_arm_adr_pcrel_12: 712 case ARM::fixup_arm_uncondbl: 713 case ARM::fixup_arm_condbl: 714 case ARM::fixup_arm_blx: 715 case ARM::fixup_arm_condbranch: 716 case ARM::fixup_arm_uncondbranch: 717 case ARM::fixup_t2_ldst_pcrel_12: 718 case ARM::fixup_t2_condbranch: 719 case ARM::fixup_t2_uncondbranch: 720 case ARM::fixup_t2_pcrel_10: 721 case ARM::fixup_t2_adr_pcrel_12: 722 case ARM::fixup_arm_thumb_bl: 723 case ARM::fixup_arm_thumb_blx: 724 case ARM::fixup_arm_movt_hi16: 725 case ARM::fixup_arm_movw_lo16: 726 case ARM::fixup_t2_movt_hi16: 727 case ARM::fixup_t2_movw_lo16: 728 // Instruction size is 4 bytes. 729 return 4; 730 } 731 } 732 733 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 734 unsigned DataSize, uint64_t Value, 735 bool IsPCRel) const { 736 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 737 Value = adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian); 738 if (!Value) return; // Doesn't change encoding. 739 740 unsigned Offset = Fixup.getOffset(); 741 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 742 743 // Used to point to big endian bytes. 744 unsigned FullSizeBytes; 745 if (!IsLittleEndian) { 746 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind()); 747 assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!"); 748 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!"); 749 } 750 751 // For each byte of the fragment that the fixup touches, mask in the bits from 752 // the fixup value. The Value has been "split up" into the appropriate 753 // bitfields above. 754 for (unsigned i = 0; i != NumBytes; ++i) { 755 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i); 756 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 757 } 758 } 759 760 namespace { 761 // FIXME: This should be in a separate file. 762 class ARMWinCOFFAsmBackend : public ARMAsmBackend { 763 public: 764 ARMWinCOFFAsmBackend(const Target &T, const StringRef &Triple) 765 : ARMAsmBackend(T, Triple, true) { } 766 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { 767 return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false); 768 } 769 }; 770 771 // FIXME: This should be in a separate file. 772 // ELF is an ELF of course... 773 class ELFARMAsmBackend : public ARMAsmBackend { 774 public: 775 uint8_t OSABI; 776 ELFARMAsmBackend(const Target &T, const StringRef TT, 777 uint8_t OSABI, bool IsLittle) 778 : ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) { } 779 780 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { 781 return createARMELFObjectWriter(OS, OSABI, isLittle()); 782 } 783 }; 784 785 // FIXME: This should be in a separate file. 786 class DarwinARMAsmBackend : public ARMAsmBackend { 787 public: 788 const MachO::CPUSubTypeARM Subtype; 789 DarwinARMAsmBackend(const Target &T, const StringRef TT, 790 MachO::CPUSubTypeARM st) 791 : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) { 792 HasDataInCodeSupport = true; 793 } 794 795 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { 796 return createARMMachObjectWriter(OS, /*Is64Bit=*/false, 797 MachO::CPU_TYPE_ARM, 798 Subtype); 799 } 800 }; 801 802 } // end anonymous namespace 803 804 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, 805 const MCRegisterInfo &MRI, 806 StringRef TT, StringRef CPU, 807 bool isLittle) { 808 Triple TheTriple(TT); 809 810 switch (TheTriple.getObjectFormat()) { 811 default: llvm_unreachable("unsupported object format"); 812 case Triple::MachO: { 813 MachO::CPUSubTypeARM CS = 814 StringSwitch<MachO::CPUSubTypeARM>(TheTriple.getArchName()) 815 .Cases("armv4t", "thumbv4t", MachO::CPU_SUBTYPE_ARM_V4T) 816 .Cases("armv5e", "thumbv5e", MachO::CPU_SUBTYPE_ARM_V5TEJ) 817 .Cases("armv6", "thumbv6", MachO::CPU_SUBTYPE_ARM_V6) 818 .Cases("armv6m", "thumbv6m", MachO::CPU_SUBTYPE_ARM_V6M) 819 .Cases("armv7em", "thumbv7em", MachO::CPU_SUBTYPE_ARM_V7EM) 820 .Cases("armv7k", "thumbv7k", MachO::CPU_SUBTYPE_ARM_V7K) 821 .Cases("armv7m", "thumbv7m", MachO::CPU_SUBTYPE_ARM_V7M) 822 .Cases("armv7s", "thumbv7s", MachO::CPU_SUBTYPE_ARM_V7S) 823 .Default(MachO::CPU_SUBTYPE_ARM_V7); 824 825 return new DarwinARMAsmBackend(T, TT, CS); 826 } 827 case Triple::COFF: 828 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); 829 return new ARMWinCOFFAsmBackend(T, TT); 830 case Triple::ELF: 831 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); 832 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); 833 return new ELFARMAsmBackend(T, TT, OSABI, isLittle); 834 } 835 } 836 837 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, 838 const MCRegisterInfo &MRI, 839 StringRef TT, StringRef CPU) { 840 return createARMAsmBackend(T, MRI, TT, CPU, true); 841 } 842 843 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, 844 const MCRegisterInfo &MRI, 845 StringRef TT, StringRef CPU) { 846 return createARMAsmBackend(T, MRI, TT, CPU, false); 847 } 848 849 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, 850 const MCRegisterInfo &MRI, 851 StringRef TT, StringRef CPU) { 852 return createARMAsmBackend(T, MRI, TT, CPU, true); 853 } 854 855 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, 856 const MCRegisterInfo &MRI, 857 StringRef TT, StringRef CPU) { 858 return createARMAsmBackend(T, MRI, TT, CPU, false); 859 } 860 861
