| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 89 int DestReg = MI->getOperand(0).getReg();
93 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
95 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
102 int DestReg = MI->getOperand(0).getReg();
106 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
108 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
115 int DestReg = MI->getOperand(0).getReg();
119 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
121 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
128 int DestReg = MI->getOperand(0).getReg()
[all...] |
| HexagonSplitTFRCondSets.cpp | 98 int DestReg = MI->getOperand(0).getReg();
114 if (DestReg != SrcReg1) {
116 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
118 if (DestReg != SrcReg2) {
120 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
128 int DestReg = MI->getOperand(0).getReg();
133 if (DestReg != SrcReg1) {
135 TII->get(Hexagon::TFR_cPt), DestReg).
140 TII->get(Hexagon::TFRI_cNotPt), DestReg).
145 TII->get(Hexagon::TFRI_cNotPt_f), DestReg)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 42 unsigned DestReg, unsigned SrcReg,
44 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
80 unsigned DestReg, int FI,
84 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
85 isARMLowRegister(DestReg))) && "Unknown regclass!");
88 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
89 isARMLowRegister(DestReg))) {
100 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
|
| Thumb2RegisterInfo.h | 32 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
|
| Thumb1InstrInfo.h | 43 unsigned DestReg, unsigned SrcReg,
53 unsigned DestReg, int FrameIndex,
|
| Thumb2RegisterInfo.cpp | 38 unsigned DestReg, unsigned SubIdx,
50 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| Thumb2InstrInfo.cpp | 115 unsigned DestReg, unsigned SrcReg,
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
119 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
170 unsigned DestReg, int FI,
186 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
204 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
[all...] |
| Thumb1RegisterInfo.cpp | 65 unsigned DestReg, unsigned SubIdx,
77 .addReg(DestReg, getDefRegState(true), SubIdx)
84 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
91 unsigned DestReg, unsigned BaseReg,
97 bool isHigh = !isARMLowRegister(DestReg) ||
108 unsigned LdReg = DestReg;
109 if (DestReg == ARM::SP) {
129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
132 if (DestReg == ARM::SP || isSub)
164 /// a destreg = basereg + immediate in Thumb code
[all...] |
| Thumb2InstrInfo.h | 44 unsigned DestReg, unsigned SrcReg,
55 unsigned DestReg, int FrameIndex,
|
| Thumb1RegisterInfo.h | 40 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
|
| SIInstrInfo.h | 35 unsigned DestReg, unsigned SrcReg,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
|
| SIInstrInfo.h | 35 unsigned DestReg, unsigned SrcReg,
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 37 unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
39 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
46 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
49 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
52 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
55 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
58 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
61 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
69 unsigned &DestReg) const {
84 DestReg = dest.getReg()
[all...] |
| NVPTXInstrInfo.h | 48 * unsigned DestReg, int FrameIndex,
54 unsigned DestReg, unsigned SrcReg, bool KillSrc) const override;
56 unsigned &DestReg) const;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 57 unsigned DestReg, unsigned SrcReg,
68 unsigned DestReg, int FrameIdx,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 80 unsigned DestReg, unsigned SrcReg,
91 unsigned DestReg, int FrameIndex,
|
| SparcInstrInfo.cpp | 283 unsigned DestReg, unsigned SrcReg,
295 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
296 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
298 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
299 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
301 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
303 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
311 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
314 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
338 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i])
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 67 unsigned DestReg, unsigned SrcReg,
78 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 273 unsigned DestReg = MI->getOperand(0).getReg();
274 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
275 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
277 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
279 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
281 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
283 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
362 unsigned DestReg = MI->getOperand(DstIndex).getReg();
369 MO.getReg() == DestReg)
372 // Constrains the regclass of DestReg to assign it to Slo
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 84 unsigned DestReg, unsigned SrcReg,
89 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
110 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
118 if (Mips::CCRRegClass.contains(DestReg))
120 else if (Mips::FGR32RegClass.contains(DestReg))
122 else if (Mips::HI32RegClass.contains(DestReg))
123 Opc = Mips::MTHI, DestReg = 0;
124 else if (Mips::LO32RegClass.contains(DestReg))
125 Opc = Mips::MTLO, DestReg = 0;
126 else if (Mips::HI32DSPRegClass.contains(DestReg))
[all...] |
| MipsInstrInfo.h | 100 unsigned DestReg, int FrameIndex,
103 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
115 unsigned DestReg, int FrameIndex,
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 240 unsigned DestReg) {
242 .addReg(DestReg, RegState::Define);
253 unsigned DestReg) {
257 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
264 unsigned DestReg) {
268 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
275 unsigned DestReg) {
278 return BuildMI(BB, MII, DL, MCID, DestReg);
282 return BuildMI(BB, MII, DL, MCID, DestReg);
339 unsigned DestReg) {
[all...] |
