| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 26 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
27 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 29 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 28 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 66 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
67 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 68 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
69 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 68 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
69 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 73 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
74 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 81 dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
82 dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 30 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
31 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 31 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
32 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 30 dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
31 dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/chromium_org/v8/src/mips64/ |
| builtins-mips64.cc | 353 __ dsll32(a0, a0, 0);
551 __ dsll32(a0, a3, 0);
788 __ dsll32(a3, a3, 0); // int32_t -> int64_t.
[all...] |
| macro-assembler-mips64.h | [all...] |
| macro-assembler-mips64.cc | 1068 dsll32(scratch, scratch, 0);
[all...] |
| assembler-mips64.h | 811 void dsll32(Register rt, Register rd, uint16_t sa);
[all...] |
| assembler-mips64.cc | 1765 void Assembler::dsll32(Register rd, Register rt, uint16_t sa) { function in class:v8::Assembler
[all...] |
| lithium-codegen-mips64.cc | [all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-mips64.cc | 172 __ dsll32(a7, a7, 0);
173 __ dsll32(t3, t3, 0);
805 __ dsll32(a6, a5, 0); // Move a5 to high bits of a6.
[all...] |
| /external/chromium_org/v8/src/ic/mips64/ |
| ic-mips64.cc | 498 __ dsll32(a3, a0, 0);
[all...] |
