| /art/compiler/dex/quick/mips/ |
| utility_mips.cc | 25 LIR* MipsMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
28 DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble());
33 if (r_src.IsSingle()) {
37 RegStorage t_opnd = r_src;
38 r_src = r_dest;
43 DCHECK(r_src.IsSingle());
47 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_src.GetReg(), r_dest.GetReg());
48 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
334 LIR* MipsMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
339 LIR* MipsMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
[all...] |
| int_mips.cc | 163 LIR* MipsMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) {
168 if (r_src.IsPair()) {
169 r_src = r_src.GetLow();
171 if (r_dest.IsFloat() || r_src.IsFloat())
172 return OpFpRegCopy(r_dest, r_src);
174 r_dest.GetReg(), r_src.GetReg());
175 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
181 void MipsMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) {
182 if (r_dest != r_src) {
[all...] |
| codegen_mips.h | 41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
46 LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src);
141 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
147 void OpRegCopy(RegStorage r_dest, RegStorage r_src);
148 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
152 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
153 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
164 // TODO: collapse r_src.
165 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
[all...] |
| target_mips.cc | 509 LIR* MipsMir2Lir::GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src) {
510 DCHECK(!r_src.IsFloat()); // See RegClassForFieldLoadStore().
511 DCHECK(r_src.IsPair());
517 OpRegCopyWide(temp_value, r_src);
|
| /art/compiler/dex/quick/x86/ |
| utility_x86.cc | 29 LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
32 DCHECK(r_dest.IsFloat() || r_src.IsFloat());
33 DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble());
38 if (r_src.IsSingle()) {
44 DCHECK(r_src.IsSingle()) << "Raw: 0x" << std::hex << r_src.GetRawBits();
49 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());
50 if (r_dest == r_src) {
303 LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
305 int src = r_src.IsPair() ? r_src.GetLowReg() : r_src.GetReg()
[all...] |
| int_x86.cc | 123 LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) {
128 if (r_src.IsPair()) {
129 r_src = r_src.GetLow();
131 if (r_dest.IsFloat() || r_src.IsFloat())
132 return OpFpRegCopy(r_dest, r_src);
134 r_dest.GetReg(), r_src.GetReg());
135 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
141 void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) {
142 if (r_dest != r_src) {
[all...] |
| codegen_x86.h | 78 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
80 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
268 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
274 void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
275 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE;
279 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE;
280 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
413 RegStorage r_src, OpSize size);
[all...] |
| /art/compiler/dex/quick/arm/ |
| utility_arm.cc | 380 LIR* ArmMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
385 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
758 LIR* ArmMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src,
760 bool all_low_regs = r_base.Low8() && r_index.Low8() && r_src.Low8();
766 if (r_src.IsFloat()) {
767 if (r_src.IsSingle()) {
772 DCHECK(r_src.IsDouble());
774 DCHECK_EQ((r_src.GetReg() & 0x1), 0);
794 store = NewLIR3(opcode, r_src.GetReg(), reg_ptr.GetReg(), 0);
816 store = NewLIR3(opcode, r_src.GetReg(), r_base.GetReg(), r_index.GetReg())
[all...] |
| codegen_arm.h | 41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
143 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
150 void OpRegCopy(RegStorage r_dest, RegStorage r_src);
151 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
155 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
156 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
165 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
212 void GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops);
|
| int_arm.cc | 401 LIR* ArmMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) {
408 if (r_src.IsPair()) {
409 r_src = r_src.GetLow();
411 if (r_dest.IsFloat() || r_src.IsFloat())
412 return OpFpRegCopy(r_dest, r_src);
413 if (r_dest.Low8() && r_src.Low8())
415 else if (!r_dest.Low8() && !r_src.Low8())
421 res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());
422 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
[all...] |
| /art/compiler/dex/quick/arm64/ |
| utility_arm64.cc | 685 LIR* Arm64Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
690 LIR* Arm64Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
[all...] |
| codegen_arm64.h | 85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
87 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile)
89 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
91 LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) OVERRIDE;
209 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
215 void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
216 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE;
220 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE;
221 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
380 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size)
[all...] |
| int_arm64.cc | 301 LIR* Arm64Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) {
303 bool src_is_fp = r_src.IsFloat();
309 DCHECK_EQ(r_dest.Is64Bit(), r_src.Is64Bit());
320 if (r_dest.Is64Bit() && r_src.Is64Bit()) {
326 bool src_is_double = r_src.IsDouble();
340 r_src = Check32BitReg(r_src);
344 if (r_src.IsDouble()) {
353 res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());
355 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
[all...] |
| /external/libnl/lib/route/ |
| rule.c | 52 nl_addr_put(rule->r_src);
61 if (src->r_src)
62 if (!(dst->r_src = nl_addr_clone(src->r_src)))
117 if (!(rule->r_src = nl_addr_alloc_attr(tb[RTA_SRC], family)))
119 nl_addr_set_prefixlen(rule->r_src, r->rtm_src_len);
182 nl_addr2str(r->r_src, buf, sizeof(buf)));
248 nl_addr2str(rule->r_src, buf, sizeof(buf)));
295 diff |= RULE_DIFF(SRC, nl_addr_cmp(a->r_src, b->r_src));
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_ppc_isel.c | 480 static PPCInstr* mk_iMOVds_RR ( HReg r_dst, HReg r_src )
482 vassert(hregClass(r_dst) == hregClass(r_src));
483 vassert(hregClass(r_src) == HRcInt32 ||
484 hregClass(r_src) == HRcInt64);
485 return PPCInstr_Alu(Palu_OR, r_dst, r_src, PPCRH_Reg(r_src));
556 static HReg mk_LoadR64toFPR ( ISelEnv* env, HReg r_src )
562 vassert(hregClass(r_src) == HRcInt64);
568 addInstr(env, PPCInstr_Store( 8, am_addr0, r_src, env->mode64 ));
1137 HReg r_src; local
1229 HReg r_src; local
1820 HReg r_src = iselWordExpr_R(env, expr32); local
1848 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1857 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1871 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1884 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1897 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1912 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1923 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1949 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
2010 HReg r_src, r_dst; local
2026 HReg r_src, r_dst; local
2038 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
2048 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
2841 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
2894 HReg r_src = lookupIRTemp(env, e->Iex.RdTmp.tmp); local
3862 HReg r_src = newVRegI(env); local
3952 HReg r_src = iselDblExpr(env, e->Iex.Binop.arg2); local
4046 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
4211 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
4476 HReg r_src = iselDfp64Expr(env, e->Iex.Unop.arg); local
4814 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
5114 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1); local
5125 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1); local
5136 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1); local
5147 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1); local
5158 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1); local
5288 HReg r_src = iselWordExpr_R(env, stmt->Ist.Store.data); local
5358 HReg r_src = iselWordExpr_R(env, stmt->Ist.Put.data); local
5422 HReg r_src = iselWordExpr_R(env, puti->data); local
5428 HReg r_src = iselWordExpr_R(env, puti->data); local
5443 HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data); local
5559 HReg r_src = iselWordExpr_R(env, stmt->Ist.LLSC.storedata); local
[all...] |
| host_mips_isel.c | 325 static MIPSInstr *mk_iMOVds_RR(HReg r_dst, HReg r_src)
327 vassert(hregClass(r_dst) == hregClass(r_src));
328 vassert(hregClass(r_src) == HRcInt32 || hregClass(r_src) == HRcInt64);
329 return MIPSInstr_Alu(Malu_OR, r_dst, r_src, MIPSRH_Reg(r_src));
1377 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1502 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1511 HReg r_src, r_dst; local
1522 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1537 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1568 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1580 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1612 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1623 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1635 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1644 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1663 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1677 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
1686 HReg r_src; local
3050 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
3473 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); local
3648 HReg r_src = iselWordExpr_R(env, stmt->Ist.Store.data); local
3693 HReg r_src = iselWordExpr_R(env, stmt->Ist.Put.data); local
3743 HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data); local
3751 HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data); local
3918 HReg r_src = iselWordExpr_R(env, stmt->Ist.LLSC.storedata); local
[all...] |
| host_mips_defs.c | 3070 UInt r_src = iregNo(i->Min.Unary.src, mode64); local
3234 UInt r_src = iregNo(i->Min.MtHL.src, mode64); local
3240 UInt r_src = iregNo(i->Min.MtHL.src, mode64); local
3258 UInt r_src = iregNo(i->Min.MtFCSR.src, mode64); local
3315 UInt r_src = iregNo(i->Min.Call.src, mode64); local
3572 UInt r_src = iregNo(i->Min.Store.src, mode64); local
3599 UInt r_src = iregNo(i->Min.Store.src, mode64); local
3627 UInt r_src = iregNo(am_addr->Mam.IR.base, mode64); local
3639 UInt r_src = iregNo(i->Min.StoreC.src, mode64); local
[all...] |
| guest_x86_toIR.c | 3849 UInt r_src, r_dst; local
[all...] |
| host_ppc_defs.c | 3990 UInt r_src = iregNo(i->Pin.Unary.src, mode64); local
4310 UInt r_dst, r_src; local
4443 UInt r_src = iregNo(i->Pin.Store.src, mode64); local
[all...] |
| guest_amd64_toIR.c | 5340 UInt r_src, r_dst; local
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | [all...] |
| gen_common.cc | 443 RegStorage r_src = AllocTempRef(); local
464 OpRegRegImm(kOpAdd, r_src, TargetPtrReg(kSp), SRegOffset(rl_first.s_reg_low));
475 LoadBaseIndexed(r_src, r_idx, r_val, 2, k32);
[all...] |
| /external/libnl/include/ |
| netlink-types.h | 295 struct nl_addr *r_src; member in struct:rtnl_rule
|
