| /prebuilts/gcc/darwin-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/ |
| msa.h | 31 typedef signed char v16i8 __attribute__((vector_size(16), aligned(16))); typedef
53 extern v16i8 __builtin_msa_sll_b(v16i8, v16i8);
61 extern v16i8 __builtin_msa_slli_b(v16i8, unsigned char);
69 extern v16i8 __builtin_msa_sra_b(v16i8, v16i8);
77 extern v16i8 __builtin_msa_srai_b(v16i8, unsigned char)
[all...] |
| /prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/ |
| msa.h | 31 typedef signed char v16i8 __attribute__((vector_size(16), aligned(16))); typedef
53 extern v16i8 __builtin_msa_sll_b(v16i8, v16i8);
61 extern v16i8 __builtin_msa_slli_b(v16i8, unsigned char);
69 extern v16i8 __builtin_msa_sra_b(v16i8, v16i8);
77 extern v16i8 __builtin_msa_srai_b(v16i8, unsigned char)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SITypeRewriter.cpp | 14 /// v16i8 => i128
15 /// - v16i8 is used for constant memory resource descriptors. This type is
17 /// in the backend, because we want the legalizer to expand all v16i8
37 Type *v16i8; member in class:__anon9828::SITypeRewriter
58 v16i8 = VectorType::get(Type::getInt8Ty(M.getContext()), 16);
86 if (ElemTy == v16i8) {
111 if (Arg->getType() == v16i8) {
|
| SIISelLowering.cpp | 135 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 259 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
264 { ISD::SRL, MVT::v16i8, 1 }, // psrlw.
269 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
314 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
320 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
325 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
336 { ISD::SDIV, MVT::v16i8, 16*20 },
340 { ISD::UDIV, MVT::v16i8, 16*20 },
468 // There is no instruction that matches a v16i8 alternate shuffle.
470 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 3
[all...] |
| X86ISelLowering.cpp | [all...] |
| X86FastISel.cpp | 469 case MVT::v16i8:
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 69 v16i8 = 23, // 16 x i8 enumerator in enum:llvm::MVT::SimpleValueType
211 return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 ||
278 case v16i8:
322 case v16i8:
409 case v16i8:
522 if (NumElements == 16) return MVT::v16i8;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| AArch64ISelLowering.cpp | 100 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
112 addQRTypeForNEON(MVT::v16i8);
528 if (VT != MVT::v8i8 && VT != MVT::v16i8)
612 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 231 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
232 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
235 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
462 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 2}};
488 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 32}};
543 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
544 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
545 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
546 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
|
| ARMISelDAGToDAG.cpp | [all...] |
| ARMISelLowering.cpp | 433 addQRTypeForNEON(MVT::v16i8);
537 // v8i8/v16i8 vcnt instruction.
[all...] |
| /external/clang/test/CodeGen/ |
| builtins-mips-msa.c | 5 typedef signed char v16i8 __attribute__ ((vector_size(16))); typedef
18 v16i8 v16i8_a = (v16i8) {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
19 v16i8 v16i8_b = (v16i8) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
20 v16i8 v16i8_r;
[all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 141 case MVT::v16i8: return "v16i8";
209 case MVT::v16i8: return VectorType::get(Type::getInt8Ty(Context), 16);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 72 DecodePALIGNRMask(MVT::v16i8,
165 DecodeUNPCKHMask(MVT::v16i8, ShuffleMask);
238 DecodeUNPCKLMask(MVT::v16i8, ShuffleMask);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 411 // We promote all shuffles to v16i8.
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
[all...] |
| PPCISelDAGToDAG.cpp | 652 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
660 if (VecVT == MVT::v16i8)
676 if (VecVT == MVT::v16i8)
691 if (VecVT == MVT::v16i8)
726 // types (v16i8, v8i16, v4i32, and v4f32).
729 case MVT::v16i8:
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 211 else if (RC->hasType(MVT::v16i8))
252 else if (RC->hasType(MVT::v16i8))
|
| MipsSEISelDAGToDAG.cpp | 829 ViaVecTy = MVT::v16i8;
|
| MipsSEISelLowering.cpp | 89 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
[all...] |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 82 case MVT::v16i8: return "MVT::v16i8";
|
