| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 437 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
449 unsigned DestReg = MI.getOperand(0).getReg();
450 assert(MI.definesRegister(DestReg) &&
458 if (DestReg != PPC::CR0) {
462 unsigned ShiftBits = getEncodingValue(DestReg)*4;
469 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
553 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
565 unsigned DestReg = MI.getOperand(0).getReg();
566 assert(MI.definesRegister(DestReg) &&
572 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
[all...] |
| PPCFastISel.cpp | 144 bool isZExt, unsigned DestReg);
153 unsigned DestReg, bool IsZExt);
734 bool IsZExt, unsigned DestReg) {
818 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
821 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
859 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
860 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg)
863 UpdateValueMap(I, DestReg);
[all...] |
| /external/llvm/lib/CodeGen/ |
| PHIElimination.cpp | 231 unsigned DestReg = MPhi->getOperand(0).getReg();
248 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
260 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
264 TII->get(TargetOpcode::COPY), DestReg)
302 LV->addVirtualRegisterDead(DestReg, PHICopy);
303 LV->removeVirtualRegisterDead(DestReg, MPhi);
326 LiveInterval &DestLI = LIS->getInterval(DestReg);
341 // instruction from DestReg's live interval.
|
| LiveRangeEdit.cpp | 150 unsigned DestReg,
155 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
|
| TargetInstrInfo.cpp | 316 unsigned DestReg,
321 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.h | 45 unsigned DestReg, unsigned SrcReg,
|
| AMDGPUInstrInfo.cpp | 134 unsigned DestReg, int FrameIndex,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.h | 45 unsigned DestReg, unsigned SrcReg,
|
| AMDGPUInstrInfo.cpp | 134 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 38 unsigned DestReg, unsigned SrcReg,
44 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
73 if (AMDGPU::M0 == DestReg) {
93 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
95 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
99 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
101 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
105 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
110 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
115 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
[all...] |
| R600InstrInfo.cpp | 51 unsigned DestReg, unsigned SrcReg,
54 if ((AMDGPU::R600_Reg128RegClass.contains(DestReg) ||
55 AMDGPU::R600_Reg128VerticalRegClass.contains(DestReg)) &&
59 } else if((AMDGPU::R600_Reg64RegClass.contains(DestReg) ||
60 AMDGPU::R600_Reg64VerticalRegClass.contains(DestReg)) &&
70 RI.getSubReg(DestReg, SubRegIndex),
72 .addReg(DestReg,
77 DestReg, SrcReg);
[all...] |
| AMDGPUInstrInfo.cpp | 118 unsigned DestReg, int FrameIndex,
|
| R600InstrInfo.h | 66 unsigned DestReg, unsigned SrcReg,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
118 VRBase = DestReg;
120 } else if (DestReg != SrcReg)
159 // Figure out the register class to create for the destreg.
473 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
474 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
475 VRBase = DestReg;
513 // Create the destreg if it is missing.
528 // Figure out the register class to create for the destreg. It should b
[all...] |
| FunctionLoweringInfo.cpp | 322 unsigned DestReg = ValueMap[PN];
323 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
325 LiveOutRegInfo.grow(DestReg);
326 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
|
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 484 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
486 TII.get(Opc), DestReg).addImm(Imm));
487 return DestReg;
500 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
505 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
508 return DestReg;
549 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
561 TII.get(ARM::t2LDRpci), DestReg)
565 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0)
[all...] |
| ARMBaseRegisterInfo.h | 171 DebugLoc dl, unsigned DestReg, unsigned SubIdx,
|
| ARMBaseRegisterInfo.cpp | 401 unsigned DestReg, unsigned SubIdx, int Val,
412 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 215 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
219 unsigned DestReg, unsigned SubIdx,
516 unsigned DestReg, unsigned SrcReg,
541 unsigned DestReg, int FrameIndex,
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveRangeEdit.h | 187 /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
193 unsigned DestReg,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64LoadStoreOptimizer.cpp | 646 unsigned DestReg = MemMI->getOperand(0).getReg();
653 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
701 unsigned DestReg = MemMI->getOperand(0).getReg();
712 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
[all...] |
| AArch64ConditionalCompares.cpp | 595 unsigned DestReg =
599 .addReg(DestReg, RegState::Define | RegState::Dead)
|
| AArch64FastISel.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 774 unsigned RdhwrOpc, DestReg;
778 DestReg = Mips::V1;
781 DestReg = Mips::V1_64;
788 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
790 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
