| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
87 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
|
| /external/llvm/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | 851 case TargetOpcode::INLINEASM: {
859 case TargetOpcode::CFI_INSTRUCTION:
861 case TargetOpcode::EH_LABEL:
864 case TargetOpcode::IMPLICIT_DEF:
865 case TargetOpcode::KILL:
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMFastISel.cpp | 302 TII.get(TargetOpcode::COPY), ResultReg)
330 TII.get(TargetOpcode::COPY), ResultReg)
362 TII.get(TargetOpcode::COPY), ResultReg)
388 TII.get(TargetOpcode::COPY), ResultReg)
418 TII.get(TargetOpcode::COPY), ResultReg)
437 TII.get(TargetOpcode::COPY), ResultReg)
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 771 case TargetOpcode::CFI_INSTRUCTION:
775 case TargetOpcode::EH_LABEL:
776 case TargetOpcode::GC_LABEL:
779 case TargetOpcode::INLINEASM:
782 case TargetOpcode::DBG_VALUE:
788 case TargetOpcode::IMPLICIT_DEF:
791 case TargetOpcode::KILL:
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 50 case TargetOpcode::DBG_VALUE:
51 case TargetOpcode::EH_LABEL:
52 case TargetOpcode::IMPLICIT_DEF:
53 case TargetOpcode::KILL:
987 case TargetOpcode::COPY:
999 case TargetOpcode::COPY: {
[all...] |
| AArch64ISelDAGToDAG.cpp | 527 MachineSDNode *Node = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
667 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, SDLoc(N), MVT::i64),
670 TargetOpcode::INSERT_SUBREG, SDLoc(N), MVT::i64, ImpDef, N, SubReg);
874 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| PPCRegisterInfo.cpp | 524 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
572 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
818 else if (OpC != TargetOpcode::INLINEASM) {
[all...] |
| PPCInstrInfo.cpp | 680 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 82 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
794 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
798 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
844 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 787 case TargetOpcode::DBG_VALUE:
[all...] |
| X86FloatingPoint.cpp | [all...] |
| X86RegisterInfo.cpp | 506 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
|
| /external/llvm/lib/CodeGen/ |
| GCStrategy.cpp | 349 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
|
| LiveRangeEdit.cpp | 303 MI->setDesc(TII.get(TargetOpcode::KILL));
|
| MachineRegisterInfo.cpp | 381 TII.get(TargetOpcode::COPY), LiveIns[i].second)
|
| TwoAddressInstructionPass.cpp | [all...] |
| VirtRegMap.cpp | 400 MI->setDesc(TII->get(TargetOpcode::KILL));
|
| LiveDebugVariables.cpp | [all...] |
| RegAllocFast.cpp | 313 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE))
870 TII->get(TargetOpcode::DBG_VALUE)
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 98 if (Opcode == TargetOpcode::COPY_TO_REGCLASS)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 213 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcAsmPrinter.cpp | 263 case TargetOpcode::DBG_VALUE:
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | [all...] |
