1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _PSB_DRM_H_ 20 #define _PSB_DRM_H_ 21 #if defined(__linux__) && !defined(__KERNEL__) 22 #include <stdbool.h> 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #include <stdint.h> 25 #include <linux/types.h> 26 #include "drm_mode.h" 27 #endif 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define PSB_PACKAGE_VERSION "5.6.0.1202" 30 #define DRM_PSB_SAREA_MAJOR 0 31 #define DRM_PSB_SAREA_MINOR 2 32 #define PSB_FIXED_SHIFT 16 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define PSB_NUM_PIPE 3 35 #define DRM_PSB_MEM_MMU TTM_PL_PRIV1 36 #define DRM_PSB_FLAG_MEM_MMU TTM_PL_FLAG_PRIV1 37 #define TTM_PL_CI TTM_PL_PRIV0 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define TTM_PL_FLAG_CI TTM_PL_FLAG_PRIV0 40 #define TTM_PL_RAR TTM_PL_PRIV2 41 #define TTM_PL_FLAG_RAR TTM_PL_FLAG_PRIV2 42 #define TTM_PL_IMR TTM_PL_PRIV2 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define TTM_PL_FLAG_IMR TTM_PL_FLAG_PRIV2 45 #define DRM_PSB_MEM_MMU_TILING TTM_PL_PRIV3 46 #define DRM_PSB_FLAG_MEM_MMU_TILING TTM_PL_FLAG_PRIV3 47 typedef enum { 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 DRM_CMD_SUCCESS, 50 DRM_CMD_FAILED, 51 DRM_CMD_HANG 52 } drm_cmd_status_t; 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 struct drm_psb_scanout { 55 uint32_t buffer_id; 56 uint32_t rotation; 57 uint32_t stride; 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 uint32_t depth; 60 uint32_t width; 61 uint32_t height; 62 int32_t transform[3][3]; 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 }; 65 #define DRM_PSB_SAREA_OWNERS 16 66 #define DRM_PSB_SAREA_OWNER_2D 0 67 #define DRM_PSB_SAREA_OWNER_3D 1 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define DRM_PSB_SAREA_SCANOUTS 3 70 struct drm_psb_sarea { 71 uint32_t major; 72 uint32_t minor; 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS]; 75 uint32_t num_scanouts; 76 struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS]; 77 int planeA_x; 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 int planeA_y; 80 int planeA_w; 81 int planeA_h; 82 int planeB_x; 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 int planeB_y; 85 int planeB_w; 86 int planeB_h; 87 uint32_t num_active_scanouts; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 }; 90 #define PSB_RELOC_MAGIC 0x67676767 91 #define PSB_RELOC_SHIFT_MASK 0x0000FFFF 92 #define PSB_RELOC_SHIFT_SHIFT 0 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000 95 #define PSB_RELOC_ALSHIFT_SHIFT 16 96 #define PSB_RELOC_OP_OFFSET 0 97 struct drm_psb_reloc { 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 uint32_t reloc_op; 100 uint32_t where; 101 uint32_t buffer; 102 uint32_t mask; 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 uint32_t shift; 105 uint32_t pre_add; 106 uint32_t background; 107 uint32_t dst_buffer; 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 uint32_t arg0; 110 uint32_t arg1; 111 }; 112 #define PSB_GPU_ACCESS_READ (1ULL << 32) 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 #define PSB_GPU_ACCESS_WRITE (1ULL << 33) 115 #define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE) 116 #define PSB_BO_FLAG_COMMAND (1ULL << 52) 117 #define PSB_ENGINE_2D 2 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 #define PSB_ENGINE_DECODE 0 120 #define PSB_ENGINE_VIDEO 0 121 #define LNC_ENGINE_ENCODE 1 122 #ifdef MERRIFIELD 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define PSB_NUM_ENGINES 7 125 #else 126 #define PSB_NUM_ENGINES 2 127 #endif 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 #define VSP_ENGINE_VPP 6 130 #define _PSB_FENCE_EXE_SHIFT 0 131 #define _PSB_FENCE_FEEDBACK_SHIFT 4 132 #define _PSB_FENCE_TYPE_EXE (1 << _PSB_FENCE_EXE_SHIFT) 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 #define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT) 135 #define PSB_FEEDBACK_OP_VISTEST (1 << 0) 136 struct drm_psb_extension_rep { 137 int32_t exists; 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 uint32_t driver_ioctl_offset; 140 uint32_t sarea_offset; 141 uint32_t major; 142 uint32_t minor; 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 uint32_t pl; 145 }; 146 #define DRM_PSB_EXT_NAME_LEN 128 147 union drm_psb_extension_arg { 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 char extension[DRM_PSB_EXT_NAME_LEN]; 150 struct drm_psb_extension_rep rep; 151 }; 152 #define PSB_NOT_FENCE (1 << 0) 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 #define PSB_MEM_CLFLUSH (1 << 1) 155 struct psb_validate_req { 156 uint64_t set_flags; 157 uint64_t clear_flags; 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 uint64_t next; 160 uint64_t presumed_gpu_offset; 161 uint32_t buffer_handle; 162 uint32_t presumed_flags; 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 uint32_t pad64; 165 uint32_t unfence_flag; 166 }; 167 struct psb_validate_rep { 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 uint64_t gpu_offset; 170 uint32_t placement; 171 uint32_t fence_type_mask; 172 }; 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 #define PSB_USE_PRESUMED (1 << 0) 175 struct psb_validate_arg { 176 uint64_t handled; 177 uint64_t ret; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 union { 180 struct psb_validate_req req; 181 struct psb_validate_rep rep; 182 } d; 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 }; 185 #define DRM_PSB_FENCE_NO_USER (1 << 0) 186 struct psb_ttm_fence_rep { 187 uint32_t handle; 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 uint32_t fence_class; 190 uint32_t fence_type; 191 uint32_t signaled_types; 192 uint32_t error; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 }; 195 typedef struct drm_psb_cmdbuf_arg { 196 uint64_t buffer_list; 197 uint64_t fence_arg; 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 uint32_t cmdbuf_handle; 200 uint32_t cmdbuf_offset; 201 uint32_t cmdbuf_size; 202 uint32_t reloc_handle; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 uint32_t reloc_offset; 205 uint32_t num_relocs; 206 uint32_t fence_flags; 207 uint32_t engine; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 } drm_psb_cmdbuf_arg_t; 210 typedef struct drm_psb_pageflip_arg { 211 uint32_t flip_offset; 212 uint32_t stride; 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 } drm_psb_pageflip_arg_t; 215 typedef enum { 216 LNC_VIDEO_DEVICE_INFO, 217 LNC_VIDEO_GETPARAM_IMR_INFO, 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 LNC_VIDEO_GETPARAM_CI_INFO, 220 LNC_VIDEO_FRAME_SKIP, 221 IMG_VIDEO_DECODE_STATUS, 222 IMG_VIDEO_NEW_CONTEXT, 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 IMG_VIDEO_RM_CONTEXT, 225 IMG_VIDEO_UPDATE_CONTEXT, 226 IMG_VIDEO_MB_ERROR, 227 IMG_VIDEO_SET_DISPLAYING_FRAME, 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 IMG_VIDEO_GET_DISPLAYING_FRAME, 230 IMG_VIDEO_GET_HDMI_STATE, 231 IMG_VIDEO_SET_HDMI_STATE, 232 PNW_VIDEO_QUERY_ENTRY, 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 IMG_DISPLAY_SET_WIDI_EXT_STATE, 235 IMG_VIDEO_IED_STATE 236 } lnc_getparam_key_t; 237 struct drm_lnc_video_getparam_arg { 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 uint64_t key; 240 uint64_t arg; 241 uint64_t value; 242 }; 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 struct drm_video_displaying_frameinfo { 245 uint32_t buf_handle; 246 uint32_t width; 247 uint32_t height; 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 uint32_t size; 250 uint32_t format; 251 uint32_t luma_stride; 252 uint32_t chroma_u_stride; 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 uint32_t chroma_v_stride; 255 uint32_t luma_offset; 256 uint32_t chroma_u_offset; 257 uint32_t chroma_v_offset; 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 uint32_t reserved; 260 }; 261 struct drm_psb_vistest { 262 uint32_t vt[8]; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 }; 265 struct drm_psb_sizes_arg { 266 uint32_t ta_mem_size; 267 uint32_t mmu_size; 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 uint32_t pds_size; 270 uint32_t rastgeom_size; 271 uint32_t tt_size; 272 uint32_t vram_size; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 }; 275 struct drm_psb_hist_status_arg { 276 uint32_t buf[32]; 277 }; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 struct drm_psb_dpst_lut_arg { 280 uint8_t lut[256]; 281 int output_id; 282 }; 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 struct mrst_timing_info { 285 uint16_t pixel_clock; 286 uint8_t hactive_lo; 287 uint8_t hblank_lo; 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 uint8_t hblank_hi:4; 290 uint8_t hactive_hi:4; 291 uint8_t vactive_lo; 292 uint8_t vblank_lo; 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 uint8_t vblank_hi:4; 295 uint8_t vactive_hi:4; 296 uint8_t hsync_offset_lo; 297 uint8_t hsync_pulse_width_lo; 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 uint8_t vsync_pulse_width_lo:4; 300 uint8_t vsync_offset_lo:4; 301 uint8_t vsync_pulse_width_hi:2; 302 uint8_t vsync_offset_hi:2; 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 uint8_t hsync_pulse_width_hi:2; 305 uint8_t hsync_offset_hi:2; 306 uint8_t width_mm_lo; 307 uint8_t height_mm_lo; 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 uint8_t height_mm_hi:4; 310 uint8_t width_mm_hi:4; 311 uint8_t hborder; 312 uint8_t vborder; 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 uint8_t unknown0:1; 315 uint8_t hsync_positive:1; 316 uint8_t vsync_positive:1; 317 uint8_t separate_sync:2; 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 uint8_t stereo:1; 320 uint8_t unknown6:1; 321 uint8_t interlaced:1; 322 } __attribute__((packed)); 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 struct gct_r10_timing_info { 325 uint16_t pixel_clock; 326 uint32_t hactive_lo:8; 327 uint32_t hactive_hi:4; 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 uint32_t hblank_lo:8; 330 uint32_t hblank_hi:4; 331 uint32_t hsync_offset_lo:8; 332 uint16_t hsync_offset_hi:2; 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 uint16_t hsync_pulse_width_lo:8; 335 uint16_t hsync_pulse_width_hi:2; 336 uint16_t hsync_positive:1; 337 uint16_t rsvd_1:3; 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 uint8_t vactive_lo:8; 340 uint16_t vactive_hi:4; 341 uint16_t vblank_lo:8; 342 uint16_t vblank_hi:4; 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 uint16_t vsync_offset_lo:4; 345 uint16_t vsync_offset_hi:2; 346 uint16_t vsync_pulse_width_lo:4; 347 uint16_t vsync_pulse_width_hi:2; 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 uint16_t vsync_positive:1; 350 uint16_t rsvd_2:3; 351 } __attribute__((packed)); 352 struct mrst_panel_descriptor_v1 { 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 uint32_t Panel_Port_Control; 355 uint32_t Panel_Power_On_Sequencing; 356 uint32_t Panel_Power_Off_Sequencing; 357 uint32_t Panel_Power_Cycle_Delay_and_Reference_Divisor; 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 struct mrst_timing_info DTD; 360 uint16_t Panel_Backlight_Inverter_Descriptor; 361 uint16_t Panel_MIPI_Display_Descriptor; 362 } __attribute__((packed)); 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 struct mrst_panel_descriptor_v2 { 365 uint32_t Panel_Port_Control; 366 uint32_t Panel_Power_On_Sequencing; 367 uint32_t Panel_Power_Off_Sequencing; 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 uint8_t Panel_Power_Cycle_Delay_and_Reference_Divisor; 370 struct mrst_timing_info DTD; 371 uint16_t Panel_Backlight_Inverter_Descriptor; 372 uint8_t Panel_Initial_Brightness; 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 uint16_t Panel_MIPI_Display_Descriptor; 375 } __attribute__((packed)); 376 union mrst_panel_rx { 377 struct { 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 uint16_t NumberOfLanes:2; 380 uint16_t MaxLaneFreq:3; 381 uint16_t SupportedVideoTransferMode:2; 382 uint16_t HSClkBehavior:1; 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 uint16_t DuoDisplaySupport:1; 385 uint16_t ECC_ChecksumCapabilities:1; 386 uint16_t BidirectionalCommunication:1; 387 uint16_t Rsvd:5; 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 } panelrx; 390 uint16_t panel_receiver; 391 } __attribute__((packed)); 392 struct gct_ioctl_arg { 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 uint8_t bpi; 395 uint8_t pt; 396 struct mrst_timing_info DTD; 397 uint32_t Panel_Port_Control; 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 uint32_t PP_On_Sequencing; 400 uint32_t PP_Off_Sequencing; 401 uint32_t PP_Cycle_Delay; 402 uint16_t Panel_Backlight_Inverter_Descriptor; 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 uint16_t Panel_MIPI_Display_Descriptor; 405 } __attribute__((packed)); 406 struct gct_timing_desc_block { 407 uint16_t clock; 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 uint16_t hactive:12; 410 uint16_t hblank:12; 411 uint16_t hsync_start:10; 412 uint16_t hsync_end:10; 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 uint16_t hsync_polarity:1; 415 uint16_t h_reversed:3; 416 uint16_t vactive:12; 417 uint16_t vblank:12; 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 uint16_t vsync_start:6; 420 uint16_t vsync_end:6; 421 uint16_t vsync_polarity:1; 422 uint16_t v_reversed:3; 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 } __packed; 425 struct gct_display_desc_block { 426 uint8_t type:2; 427 uint8_t pxiel_format:4; 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 uint8_t mode:2; 430 uint8_t frame_rate:6; 431 uint8_t reserved:2; 432 } __attribute__((packed)); 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 struct gct_dsi_desc_block { 435 uint8_t lane_count:2; 436 uint8_t lane_frequency:3; 437 uint8_t transfer_mode:2; 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 uint8_t hs_clock_behavior:1; 440 uint8_t duo_display_support:1; 441 uint8_t ecc_caps:1; 442 uint8_t bdirect_support:1; 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 uint8_t reversed:5; 445 } __packed; 446 struct gct_bkl_desc_block { 447 uint16_t frequency; 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 uint8_t max_brightness:7; 450 uint8_t polarity:1; 451 } __packed; 452 struct gct_r20_clock_desc { 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 uint8_t pre_divisor:2; 455 uint16_t divisor:9; 456 uint8_t post_divisor:4; 457 uint8_t pll_bypass:1; 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 uint8_t cck_clock_divisor:1; 460 uint8_t reserved:7; 461 } __packed; 462 struct gct_r20_panel_info { 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 uint16_t width; 465 uint16_t height; 466 } __packed; 467 struct gct_r20_panel_mode { 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 uint8_t mode:1; 470 uint16_t reserved:15; 471 } __packed; 472 struct gct_r20_dsi_desc { 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 uint8_t num_dsi_lanes:2; 475 uint16_t reserved:14; 476 } __packed; 477 struct gct_r20_panel_desc { 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 uint8_t panel_name[16]; 480 struct gct_timing_desc_block timing; 481 struct gct_r20_clock_desc clock_desc; 482 struct gct_r20_panel_info panel_info; 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 struct gct_r20_panel_mode panel_mode; 485 struct gct_r20_dsi_desc dsi_desc; 486 uint32_t early_init_seq; 487 uint32_t late_init_seq; 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 } __packed; 490 struct gct_r11_panel_desc { 491 uint8_t panel_name[16]; 492 struct gct_timing_desc_block timing; 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 struct gct_display_desc_block display; 495 struct gct_dsi_desc_block dsi; 496 struct gct_bkl_desc_block bkl; 497 uint32_t early_init_seq; 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 uint32_t late_init_seq; 500 } __packed; 501 struct gct_r10_panel_desc { 502 struct gct_timing_desc_block timing; 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 struct gct_display_desc_block display; 505 struct gct_dsi_desc_block dsi; 506 struct gct_bkl_desc_block bkl; 507 uint32_t early_init_seq; 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 uint32_t late_init_seq; 510 uint8_t reversed[4]; 511 } __packed; 512 struct intel_mid_vbt { 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 char signature[4]; 515 uint8_t revision; 516 uint8_t checksum; 517 uint16_t size; 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 uint8_t num_of_panel_desc; 520 uint8_t primary_panel_idx; 521 uint8_t secondary_panel_idx; 522 uint8_t splash_flag; 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 uint8_t reserved[4]; 525 void *panel_descs; 526 } __packed; 527 struct mrst_vbt { 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 char Signature[4]; 530 uint8_t Revision; 531 uint8_t Size; 532 uint8_t Checksum; 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 void *mrst_gct; 535 } __attribute__ ((packed)); 536 struct mrst_gct_v1 { 537 union { 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 struct { 540 uint8_t PanelType:4; 541 uint8_t BootPanelIndex:2; 542 uint8_t BootMIPI_DSI_RxIndex:2; 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 } PD; 545 uint8_t PanelDescriptor; 546 }; 547 struct mrst_panel_descriptor_v1 panel[4]; 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 union mrst_panel_rx panelrx[4]; 550 } __attribute__((packed)); 551 struct mrst_gct_v2 { 552 union { 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 struct { 555 uint8_t PanelType:4; 556 uint8_t BootPanelIndex:2; 557 uint8_t BootMIPI_DSI_RxIndex:2; 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 } PD; 560 uint8_t PanelDescriptor; 561 }; 562 struct mrst_panel_descriptor_v2 panel[4]; 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 union mrst_panel_rx panelrx[4]; 565 } __attribute__((packed)); 566 #define PSB_DC_CRTC_SAVE 0x01 567 #define PSB_DC_CRTC_RESTORE 0x02 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 #define PSB_DC_OUTPUT_SAVE 0x04 570 #define PSB_DC_OUTPUT_RESTORE 0x08 571 #define PSB_DC_CRTC_MASK 0x03 572 #define PSB_DC_OUTPUT_MASK 0x0C 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 struct drm_psb_dc_state_arg { 575 uint32_t flags; 576 uint32_t obj_id; 577 }; 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 struct drm_psb_mode_operation_arg { 580 uint32_t obj_id; 581 uint16_t operation; 582 struct drm_mode_modeinfo mode; 583 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 void *data; 585 }; 586 struct drm_psb_stolen_memory_arg { 587 uint32_t base; 588 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 uint32_t size; 590 }; 591 #define REGRWBITS_PFIT_CONTROLS (1 << 0) 592 #define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1) 593 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 #define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2) 595 #define REGRWBITS_PIPEASRC (1 << 3) 596 #define REGRWBITS_PIPEBSRC (1 << 4) 597 #define REGRWBITS_VTOTAL_A (1 << 5) 598 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 #define REGRWBITS_VTOTAL_B (1 << 6) 600 #define REGRWBITS_DSPACNTR (1 << 8) 601 #define REGRWBITS_DSPBCNTR (1 << 9) 602 #define REGRWBITS_DSPCCNTR (1 << 10) 603 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 #define REGRWBITS_SPRITE_UPDATE (1 << 11) 605 #define REGRWBITS_PIPEASTAT (1 << 12) 606 #define REGRWBITS_INT_MASK (1 << 13) 607 #define REGRWBITS_INT_ENABLE (1 << 14) 608 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 #define REGRWBITS_DISPLAY_ALL (1 << 15) 610 #define OV_REGRWBITS_OVADD (1 << 0) 611 #define OV_REGRWBITS_OGAM_ALL (1 << 1) 612 #define OVC_REGRWBITS_OVADD (1 << 2) 613 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 #define OVC_REGRWBITS_OGAM_ALL (1 << 3) 615 #define OV_REGRWBITS_WAIT_FLIP (1 << 4) 616 #define OVC_REGRWBITS_WAIT_FLIP (1 << 5) 617 #define OVSTATUS_REGRBIT_OVR_UPDT (1 << 6) 618 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 #define SPRITE_UPDATE_SURFACE (0x00000001UL) 620 #define SPRITE_UPDATE_CONTROL (0x00000002UL) 621 #define SPRITE_UPDATE_POSITION (0x00000004UL) 622 #define SPRITE_UPDATE_SIZE (0x00000008UL) 623 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 #define SPRITE_UPDATE_WAIT_VBLANK (0X00000010UL) 625 #define SPRITE_UPDATE_CONSTALPHA (0x00000020UL) 626 #define SPRITE_UPDATE_ALL (0x0000003fUL) 627 #define VSYNC_ENABLE (1 << 0) 628 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 #define VSYNC_DISABLE (1 << 1) 630 #define VSYNC_WAIT (1 << 2) 631 #define GET_VSYNC_COUNT (1 << 3) 632 struct intel_overlay_context { 633 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 uint32_t index; 635 uint32_t pipe; 636 uint32_t ovadd; 637 }; 638 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 struct intel_sprite_context { 640 uint32_t update_mask; 641 uint32_t index; 642 uint32_t pipe; 643 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 uint32_t cntr; 645 uint32_t linoff; 646 uint32_t stride; 647 uint32_t pos; 648 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 uint32_t size; 650 uint32_t keyminval; 651 uint32_t keymask; 652 uint32_t surf; 653 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 uint32_t keymaxval; 655 uint32_t tileoff; 656 uint32_t contalpa; 657 }; 658 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659 #define INTEL_SPRITE_PLANE_NUM 3 660 #define INTEL_OVERLAY_PLANE_NUM 2 661 #define INTEL_DISPLAY_PLANE_NUM 5 662 #define INTEL_MDFLD_SPRITE_PLANE_NUM 3 663 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 #define INTEL_MDFLD_OVERLAY_PLANE_NUM 2 665 #define INTEL_MDFLD_CURSOR_PLANE_NUM 3 666 #define INTEL_MDFLD_DISPLAY_PLANE_NUM 8 667 #define INTEL_MDFLD_DISPLAY_PIPE_NUM 3 668 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 #define INTEL_CTP_SPRITE_PLANE_NUM 2 670 #define INTEL_CTP_OVERLAY_PLANE_NUM 1 671 #define INTEL_CTP_CURSOR_PLANE_NUM 2 672 #define INTEL_CTP_DISPLAY_PLANE_NUM 5 673 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 #define INTEL_CTP_DISPLAY_PIPE_NUM 2 675 #define INVALID_INDEX 0xffffffff 676 struct mdfld_plane_contexts { 677 uint32_t active_primaries; 678 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 uint32_t active_sprites; 680 uint32_t active_overlays; 681 struct intel_sprite_context primary_contexts[INTEL_SPRITE_PLANE_NUM]; 682 struct intel_sprite_context sprite_contexts[INTEL_SPRITE_PLANE_NUM]; 683 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684 struct intel_overlay_context overlay_contexts[INTEL_OVERLAY_PLANE_NUM]; 685 }; 686 struct drm_psb_vsync_set_arg { 687 uint32_t vsync_operation_mask; 688 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 struct { 690 uint32_t pipe; 691 int vsync_pipe; 692 int vsync_count; 693 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 uint64_t timestamp; 695 } vsync; 696 }; 697 struct drm_psb_dc_info { 698 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 uint32_t pipe_count; 700 uint32_t primary_plane_count; 701 uint32_t sprite_plane_count; 702 uint32_t overlay_plane_count; 703 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704 uint32_t cursor_plane_count; 705 }; 706 struct drm_psb_register_rw_arg { 707 uint32_t b_force_hw_on; 708 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 uint32_t display_read_mask; 710 uint32_t display_write_mask; 711 struct { 712 uint32_t pfit_controls; 713 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 uint32_t pfit_autoscale_ratios; 715 uint32_t pfit_programmed_scale_ratios; 716 uint32_t pipeasrc; 717 uint32_t pipebsrc; 718 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719 uint32_t vtotal_a; 720 uint32_t vtotal_b; 721 uint32_t dspcntr_a; 722 uint32_t dspcntr_b; 723 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724 uint32_t pipestat_a; 725 uint32_t int_mask; 726 uint32_t int_enable; 727 } display; 728 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 uint32_t overlay_read_mask; 730 uint32_t overlay_write_mask; 731 struct { 732 uint32_t OVADD; 733 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734 uint32_t OGAMC0; 735 uint32_t OGAMC1; 736 uint32_t OGAMC2; 737 uint32_t OGAMC3; 738 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739 uint32_t OGAMC4; 740 uint32_t OGAMC5; 741 uint32_t IEP_ENABLED; 742 uint32_t IEP_BLE_MINMAX; 743 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744 uint32_t IEP_BSSCC_CONTROL; 745 uint32_t index; 746 uint32_t b_wait_vblank; 747 uint32_t b_wms; 748 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749 uint32_t buffer_handle; 750 } overlay; 751 uint32_t vsync_operation_mask; 752 struct { 753 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754 uint32_t pipe; 755 int vsync_pipe; 756 int vsync_count; 757 uint64_t timestamp; 758 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759 } vsync; 760 uint32_t sprite_enable_mask; 761 uint32_t sprite_disable_mask; 762 struct { 763 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764 uint32_t dspa_control; 765 uint32_t dspa_key_value; 766 uint32_t dspa_key_mask; 767 uint32_t dspc_control; 768 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769 uint32_t dspc_stride; 770 uint32_t dspc_position; 771 uint32_t dspc_linear_offset; 772 uint32_t dspc_size; 773 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774 uint32_t dspc_surface; 775 } sprite; 776 uint32_t subpicture_enable_mask; 777 uint32_t subpicture_disable_mask; 778 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779 struct { 780 uint32_t CursorADDR; 781 uint32_t xPos; 782 uint32_t yPos; 783 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784 uint32_t CursorSize; 785 } cursor; 786 uint32_t cursor_enable_mask; 787 uint32_t cursor_disable_mask; 788 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789 uint32_t plane_enable_mask; 790 uint32_t plane_disable_mask; 791 uint32_t get_plane_state_mask; 792 struct { 793 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794 uint32_t type; 795 uint32_t index; 796 uint32_t ctx; 797 } plane; 798 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799 }; 800 enum { 801 PSB_DC_PLANE_ENABLED, 802 PSB_DC_PLANE_DISABLED, 803 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804 }; 805 enum { 806 PSB_GTT_MAP_TYPE_MEMINFO = 0, 807 PSB_GTT_MAP_TYPE_BCD, 808 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809 PSB_GTT_MAP_TYPE_BCD_INFO, 810 PSB_GTT_MAP_TYPE_VIRTUAL, 811 }; 812 struct psb_gtt_mapping_arg { 813 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814 uint32_t type; 815 void *hKernelMemInfo; 816 uint32_t offset_pages; 817 uint32_t page_align; 818 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819 uint32_t bcd_device_id; 820 uint32_t bcd_buffer_id; 821 uint32_t bcd_buffer_count; 822 uint32_t bcd_buffer_stride; 823 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824 uint32_t vaddr; 825 uint32_t size; 826 }; 827 struct drm_psb_getpageaddrs_arg { 828 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829 uint64_t handle; 830 uint64_t page_addrs; 831 uint64_t gtt_offset; 832 }; 833 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834 #define MAX_SLICES_PER_PICTURE 72 835 struct psb_msvdx_mb_region { 836 uint32_t start; 837 uint32_t end; 838 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839 }; 840 typedef struct drm_psb_msvdx_decode_status { 841 uint32_t num_region; 842 struct psb_msvdx_mb_region mb_regions[MAX_SLICES_PER_PICTURE]; 843 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844 } drm_psb_msvdx_decode_status_t; 845 enum { 846 IDLE_CTRL_ENABLE = 0, 847 IDLE_CTRL_DISABLE, 848 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849 IDLE_CTRL_ENTER, 850 IDLE_CTRL_EXIT 851 }; 852 struct drm_psb_idle_ctrl { 853 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854 uint32_t cmd; 855 uint32_t value; 856 }; 857 #define DRM_PSB_KMS_OFF 0x00 858 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859 #define DRM_PSB_KMS_ON 0x01 860 #define DRM_PSB_VT_LEAVE 0x02 861 #define DRM_PSB_VT_ENTER 0x03 862 #define DRM_PSB_EXTENSION 0x06 863 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864 #define DRM_PSB_SIZES 0x07 865 #define DRM_PSB_FUSE_REG 0x08 866 #define DRM_PSB_VBT 0x09 867 #define DRM_PSB_DC_STATE 0x0A 868 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869 #define DRM_PSB_ADB 0x0B 870 #define DRM_PSB_MODE_OPERATION 0x0C 871 #define DRM_PSB_STOLEN_MEMORY 0x0D 872 #define DRM_PSB_REGISTER_RW 0x0E 873 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874 #define DRM_PSB_GTT_MAP 0x0F 875 #define DRM_PSB_GTT_UNMAP 0x10 876 #define DRM_PSB_GETPAGEADDRS 0x11 877 #define DRM_PVR_RESERVED1 0x12 878 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879 #define DRM_PVR_RESERVED2 0x13 880 #define DRM_PVR_RESERVED3 0x14 881 #define DRM_PVR_RESERVED4 0x15 882 #define DRM_PVR_RESERVED5 0x16 883 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884 #define DRM_PSB_HIST_ENABLE 0x17 885 #define DRM_PSB_HIST_STATUS 0x18 886 #define DRM_PSB_UPDATE_GUARD 0x19 887 #define DRM_PSB_INIT_COMM 0x1A 888 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889 #define DRM_PSB_DPST 0x1B 890 #define DRM_PSB_GAMMA 0x1C 891 #define DRM_PSB_DPST_BL 0x1D 892 #define DRM_PVR_RESERVED6 0x1E 893 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894 #define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F 895 #define DRM_PSB_DPU_QUERY 0x20 896 #define DRM_PSB_DPU_DSR_ON 0x21 897 #define DRM_PSB_DPU_DSR_OFF 0x22 898 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899 #define DRM_PSB_HDMI_FB_CMD 0x23 900 #define DRM_PSB_QUERY_HDCP 0x24 901 #define DRM_PSB_VALIDATE_HDCP_KSV 0x25 902 #define DRM_PSB_GET_HDCP_STATUS 0x26 903 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904 #define DRM_PSB_ENABLE_HDCP 0x27 905 #define DRM_PSB_DISABLE_HDCP 0x28 906 #define DRM_PSB_GET_HDCP_LINK_STATUS 0x2b 907 #define DRM_PSB_ENABLE_HDCP_REPEATER 0x2c 908 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909 #define DRM_PSB_DISABLE_HDCP_REPEATER 0x2d 910 #define DRM_PSB_HDCP_REPEATER_PRESENT 0x2e 911 #define DRM_PSB_CSC_GAMMA_SETTING 0x29 912 #define DRM_PSB_SET_CSC 0x2a 913 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 914 #define DRM_PSB_ENABLE_IED_SESSION 0x30 915 #define DRM_PSB_DISABLE_IED_SESSION 0x31 916 #define DRM_PSB_VSYNC_SET 0x32 917 #define DRM_PSB_HDCP_DISPLAY_IED_OFF 0x33 918 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 919 #define DRM_PSB_HDCP_DISPLAY_IED_ON 0x34 920 #define DRM_PSB_QUERY_HDCP_DISPLAY_IED_CAPS 0x35 921 #define DRM_PSB_DPST_LEVEL 0x36 922 #define DRM_PSB_GET_DC_INFO 0x37 923 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 924 #define DRM_PSB_PANEL_QUERY 0x38 925 #define DRM_PSB_IDLE_CTRL 0x39 926 #define DRM_PSB_HDMITEST 0x3A 927 #define HT_READ 1 928 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 929 #define HT_WRITE 2 930 #define HT_FORCEON 4 931 typedef struct tagHDMITESTREGREADWRITE { 932 unsigned int reg; 933 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 934 unsigned int data; 935 int mode; 936 } drm_psb_hdmireg_t, *drm_psb_hdmireg_p; 937 #define DRM_PSB_PANEL_ORIENTATION 0x3B 938 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 939 #define DRM_PSB_UPDATE_CURSOR_POS 0x3C 940 #define DRM_OEM_RESERVED_START 0x40 941 #define DRM_OEM_RESERVED_END 0x4F 942 #define DRM_PSB_TTM_START 0x50 943 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 944 #define DRM_PSB_TTM_END 0x5F 945 #ifdef PDUMP 946 #define DRM_PSB_CMDBUF (PVR_DRM_DBGDRV_CMD + 1) 947 #else 948 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 949 #define DRM_PSB_CMDBUF (DRM_PSB_TTM_START) 950 #endif 951 #define DRM_PSB_SCENE_UNREF (DRM_PSB_CMDBUF + 1) 952 #define DRM_PSB_PLACEMENT_OFFSET (DRM_PSB_SCENE_UNREF + 1) 953 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 954 #define DRM_PSB_DSR_ENABLE 0xfffffffe 955 #define DRM_PSB_DSR_DISABLE 0xffffffff 956 struct drm_psb_csc_matrix { 957 int pipe; 958 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 959 int64_t matrix[9]; 960 }__attribute__((packed)); 961 struct psb_drm_dpu_rect { 962 int x, y; 963 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 964 int width, height; 965 }; 966 struct drm_psb_drv_dsr_off_arg { 967 int screen; 968 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 969 struct psb_drm_dpu_rect damage_rect; 970 }; 971 struct drm_psb_dev_info_arg { 972 uint32_t num_use_attribute_registers; 973 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 974 }; 975 #define DRM_PSB_DEVINFO 0x01 976 #define PSB_MODE_OPERATION_MODE_VALID 0x01 977 #define PSB_MODE_OPERATION_SET_DC_BASE 0x02 978 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 979 struct drm_psb_get_pipe_from_crtc_id_arg { 980 uint32_t crtc_id; 981 uint32_t pipe; 982 }; 983 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 984 #define DRM_PSB_DISP_SAVE_HDMI_FB_HANDLE 1 985 #define DRM_PSB_DISP_GET_HDMI_FB_HANDLE 2 986 #define DRM_PSB_DISP_INIT_HDMI_FLIP_CHAIN 1 987 #define DRM_PSB_DISP_QUEUE_BUFFER 2 988 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 989 #define DRM_PSB_DISP_DEQUEUE_BUFFER 3 990 #define DRM_PSB_DISP_PLANEB_DISABLE 4 991 #define DRM_PSB_DISP_PLANEB_ENABLE 5 992 #define DRM_PSB_HDMI_OSPM_ISLAND_DOWN 6 993 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 994 #define DRM_PSB_HDMI_NOTIFY_HOTPLUG_TO_AUDIO 7 995 typedef enum { 996 GAMMA, 997 CSC, 998 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 999 GAMMA_INITIA, 1000 GAMMA_SETTING, 1001 GAMMA_REG_SETTING, 1002 CSC_INITIA, 1003 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1004 CSC_CHROME_SETTING, 1005 CSC_SETTING, 1006 CSC_REG_SETTING 1007 } setting_type; 1008 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1009 typedef enum { 1010 GAMMA_05 = 1, 1011 GAMMA_20, 1012 GAMMA_05_20, 1013 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1014 GAMMA_20_05, 1015 GAMMA_10 1016 } gamma_mode; 1017 #define CSC_REG_COUNT 6 1018 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1019 #define CHROME_COUNT 16 1020 #define CSC_COUNT 9 1021 struct csc_setting { 1022 uint32_t pipe; 1023 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1024 setting_type type; 1025 bool enable_state; 1026 uint32_t data_len; 1027 union { 1028 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1029 int csc_reg_data[CSC_REG_COUNT]; 1030 int chrome_data[CHROME_COUNT]; 1031 int64_t csc_data[CSC_COUNT]; 1032 } data; 1033 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1034 }; 1035 #define GAMMA_10_BIT_TABLE_COUNT 129 1036 struct gamma_setting { 1037 uint32_t pipe; 1038 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1039 setting_type type; 1040 bool enable_state; 1041 gamma_mode initia_mode; 1042 uint32_t data_len; 1043 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1044 uint32_t gamma_tableX100[GAMMA_10_BIT_TABLE_COUNT]; 1045 }; 1046 struct drm_psb_csc_gamma_setting { 1047 setting_type type; 1048 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1049 union { 1050 struct csc_setting csc_data; 1051 struct gamma_setting gamma_data; 1052 } data; 1053 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1054 }__attribute__((packed)); 1055 struct drm_psb_buffer_data { 1056 void *h_buffer; 1057 }; 1058 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1059 struct drm_psb_flip_chain_data { 1060 void **h_buffer_array; 1061 unsigned int size; 1062 }; 1063 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1064 struct drm_psb_disp_ctrl { 1065 uint32_t cmd; 1066 union { 1067 uint32_t data; 1068 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1069 struct drm_psb_buffer_data buf_data; 1070 struct drm_psb_flip_chain_data flip_chain_data; 1071 } u; 1072 }; 1073 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1074 #define S3D_MIPIA_DISPLAY 0 1075 #define S3D_HDMI_DISPLAY 1 1076 #define S3D_MIPIC_DISPLAY 2 1077 #define S3D_WIDI_DISPLAY 0xFF 1078 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1079 struct drm_psb_s3d_query { 1080 uint32_t s3d_display_type; 1081 uint32_t is_s3d_supported; 1082 uint32_t s3d_format; 1083 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1084 uint32_t mode_resolution_x; 1085 uint32_t mode_resolution_y; 1086 uint32_t mode_refresh_rate; 1087 uint32_t is_interleaving; 1088 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1089 }; 1090 struct drm_psb_s3d_premodeset { 1091 uint32_t s3d_buffer_format; 1092 }; 1093 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1094 typedef enum intel_dc_plane_types { 1095 DC_UNKNOWN_PLANE = 0, 1096 DC_SPRITE_PLANE = 1, 1097 DC_OVERLAY_PLANE, 1098 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1099 DC_PRIMARY_PLANE, 1100 DC_CURSOR_PLANE, 1101 DC_PLANE_MAX, 1102 } DC_MRFLD_PLANE_TYPE; 1103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1104 #define SPRITE_UPDATE_SURFACE (0x00000001UL) 1105 #define SPRITE_UPDATE_CONTROL (0x00000002UL) 1106 #define SPRITE_UPDATE_POSITION (0x00000004UL) 1107 #define SPRITE_UPDATE_SIZE (0x00000008UL) 1108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1109 #define SPRITE_UPDATE_WAIT_VBLANK (0X00000010UL) 1110 #define SPRITE_UPDATE_CONSTALPHA (0x00000020UL) 1111 #define SPRITE_UPDATE_ALL (0x0000003fUL) 1112 #define MRFLD_PRIMARY_COUNT 3 1113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1114 typedef struct intel_dc_overlay_ctx { 1115 uint32_t index; 1116 uint32_t pipe; 1117 uint32_t ovadd; 1118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1119 } DC_MRFLD_OVERLAY_CONTEXT; 1120 typedef struct intel_dc_cursor_ctx { 1121 uint32_t index; 1122 uint32_t pipe; 1123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1124 uint32_t cntr; 1125 uint32_t surf; 1126 uint32_t pos; 1127 } DC_MRFLD_CURSOR_CONTEXT; 1128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1129 typedef struct intel_dc_sprite_ctx { 1130 uint32_t update_mask; 1131 uint32_t index; 1132 uint32_t pipe; 1133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1134 uint32_t cntr; 1135 uint32_t linoff; 1136 uint32_t stride; 1137 uint32_t pos; 1138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1139 uint32_t size; 1140 uint32_t keyminval; 1141 uint32_t keymask; 1142 uint32_t surf; 1143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1144 uint32_t keymaxval; 1145 uint32_t tileoff; 1146 uint32_t contalpa; 1147 } DC_MRFLD_SPRITE_CONTEXT; 1148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1149 typedef struct intel_dc_primary_ctx { 1150 uint32_t update_mask; 1151 uint32_t index; 1152 uint32_t pipe; 1153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1154 uint32_t cntr; 1155 uint32_t linoff; 1156 uint32_t stride; 1157 uint32_t pos; 1158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1159 uint32_t size; 1160 uint32_t keyminval; 1161 uint32_t keymask; 1162 uint32_t surf; 1163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1164 uint32_t keymaxval; 1165 uint32_t tileoff; 1166 uint32_t contalpa; 1167 } DC_MRFLD_PRIMARY_CONTEXT; 1168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1169 typedef struct intel_dc_plane_zorder { 1170 uint32_t forceBottom[3]; 1171 uint32_t abovePrimary; 1172 } DC_MRFLD_DC_PLANE_ZORDER; 1173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1174 typedef struct intel_dc_plane_ctx { 1175 enum intel_dc_plane_types type; 1176 struct intel_dc_plane_zorder zorder; 1177 union { 1178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1179 struct intel_dc_overlay_ctx ov_ctx; 1180 struct intel_dc_sprite_ctx sp_ctx; 1181 struct intel_dc_primary_ctx prim_ctx; 1182 struct intel_dc_cursor_ctx cs_ctx; 1183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1184 } ctx; 1185 } DC_MRFLD_SURF_CUSTOM; 1186 #endif 1187
