1 #include <stdio.h> 2 #include <config.h> 3 4 double foo = -1.0; 5 double FRT1; 6 double FRT2; 7 int base256(int val) 8 { 9 /* interpret the bitstream representing val as a base 256 number for testing 10 * the parity instrs 11 */ 12 int sum = 0; 13 int scale = 1; 14 int i; 15 16 for (i = 0; i < 8; i++) { 17 int bit = val & 1; 18 sum = sum + bit * scale; 19 val <<= 1; 20 scale *= 256; 21 } 22 return sum; 23 } 24 25 void test_parity_instrs() 26 { 27 unsigned long long_word; 28 unsigned int word; 29 int i, parity; 30 31 for (i = 0; i < 50; i++) { 32 word = base256(i); 33 long_word = word; 34 __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word)); 35 printf("prtyd (%x) => parity=%x\n", i, parity); 36 __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word)); 37 printf("prtyw (%x) => parity=%x\n", i, parity); 38 } 39 } 40 41 void test_lfiwax() 42 { 43 unsigned long base; 44 45 typedef struct { 46 unsigned int hi; 47 unsigned int lo; 48 } int_pair_t; 49 50 int_pair_t *ip; 51 foo = -1024.0; 52 base = (unsigned long) &foo; 53 54 __asm__ volatile ("lfiwax %0, 0, %1":"=f" (FRT1):"r"(base)); 55 ip = (int_pair_t *) & FRT1; 56 printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo); 57 58 59 } 60 61 62 63 /* lfdp FPp, DS(RA) : load float double pair 64 ** FPp = leftmost 64 bits stored at DS(RA) 65 ** FPp+1= rightmost 64 bits stored at DS(RA) 66 ** FPp must be an even float register 67 ** 68 ** The [st|l]fdp[x] instructions were put into the "Floating-Point.Phased-Out" 69 ** category in ISA 2.06 (i.e., POWER7 timeframe). If valgrind and its 70 ** testsuite are built with -mcpu=power7 (or later), then the assembler will 71 ** not recognize those phased out instructions. 72 ** 73 */ 74 void test_double_pair_instrs() 75 { 76 #ifdef HAVE_AS_PPC_FPPO 77 typedef struct { 78 double hi; 79 double lo; 80 } dbl_pair_t; 81 82 /* the following decls are for alignment */ 83 int i; 84 dbl_pair_t dbl_pair[3]; /* must be quad word aligned */ 85 unsigned long base; 86 unsigned long offset; 87 88 for (i = 0; i < 3; i++) { 89 dbl_pair[i].hi = -1024.0 + i; 90 dbl_pair[i].lo = 1024.0 + i + 1; 91 } 92 93 __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0])); 94 __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); 95 __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); 96 printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n", 97 dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2); 98 99 100 FRT1 = 2.2048; 101 FRT2 = -4.1024; 102 __asm__ volatile ("fmr 10, %0"::"f" (FRT1)); 103 __asm__ volatile ("fmr 11, %0"::"f" (FRT2)); 104 __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1])); 105 printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n", 106 FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo); 107 108 FRT1 = 0.0; 109 FRT2 = -1.0; 110 base = (unsigned long) &dbl_pair; 111 offset = (unsigned long) &dbl_pair[1] - base; 112 __asm__ volatile ("ori 20, %0, 0"::"r" (base)); 113 __asm__ volatile ("ori 21, %0, 0"::"r" (offset)); 114 __asm__ volatile ("lfdpx 10, 20, 21"); 115 __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); 116 __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); 117 printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", 118 dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2); 119 120 FRT1 = 8.2048; 121 FRT2 = -16.1024; 122 base = (unsigned long) &dbl_pair; 123 offset = (unsigned long) &dbl_pair[2] - base; 124 __asm__ volatile ("ori 20, %0, 0"::"r" (base)); 125 __asm__ volatile ("ori 21, %0, 0"::"r" (offset)); 126 __asm__ volatile ("fmr %0, 10":"=f" (FRT1)); 127 __asm__ volatile ("fmr %0, 11":"=f" (FRT2)); 128 __asm__ volatile ("stfdpx 10, 20, 21"); 129 printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n", 130 FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo); 131 #endif 132 } 133 134 135 /* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */ 136 void test_fcpsgn() 137 { 138 double A[] = { 139 10.101010, 140 -0.0, 141 0.0, 142 -10.101010 143 }; 144 145 double B[] = { 146 11.111111, 147 -0.0, 148 0.0, 149 -11.111111 150 }; 151 152 double FRT, FRA, FRB; 153 int i, j; 154 155 for (i = 0; i < 4; i++) { 156 FRA = A[i]; 157 for (j = 0; j < 4; j++) { 158 FRB = B[j]; 159 __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA), 160 "f"(FRB)); 161 printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT); 162 } 163 } 164 } 165 166 /* b0 may be non-zero in lwarx/ldarx Power6 instrs */ 167 void test_reservation() 168 { 169 170 int RT; 171 unsigned long base; 172 unsigned long offset; 173 long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad }; 174 175 176 base = (unsigned long) &arr; 177 offset = (unsigned long) &arr[1] - base; 178 __asm__ volatile ("ori 20, %0, 0"::"r" (base)); 179 __asm__ volatile ("ori 21, %0, 0"::"r" (offset)); 180 __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT)); 181 printf("lwarx => %x\n", RT); 182 183 #ifdef __powerpc64__ 184 offset = (unsigned long) &arr[1] - base; 185 __asm__ volatile ("ori 21, %0, 0"::"r" (offset)); 186 __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT)); 187 printf("ldarx => %x\n", RT); 188 #endif 189 190 } 191 192 int main(void) 193 { 194 (void) test_reservation(); 195 test_fcpsgn(); 196 (void) test_double_pair_instrs(); 197 test_lfiwax(); 198 test_parity_instrs(); 199 return 0; 200 } 201
