| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 794 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits
804 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
809 Ops[4].getAsInteger(10, Op2);
810 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
849 uint32_t Op2 = Bits & 0x7;
862 + "_c" + utostr(CRm) + "_" + utostr(Op2);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 300 MachineOperand Op2 = MI->getOperand(S2);
301 ChangeOpInto(MI->getOperand(S1), Op2);
|
| HexagonHardwareLoops.cpp | 524 const MachineOperand &Op2 = CondI->getOperand(2);
528 if (Op2.isImm() || Op1.getReg() == IVReg)
529 EndValue = &Op2;
[all...] |
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 254 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
267 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
272 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
282 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
360 unsigned Op1, Op2;
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
373 unsigned Op1, Op2;
374 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
379 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder)
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 72 const MCOperand &Op2 = MI->getOperand(2);
77 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
113 if (Op2.isImm() && Op3.isImm()) {
116 int64_t immr = Op2.getImm();
147 if (Op2.getImm() > Op3.getImm()) {
150 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
158 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
165 const MCOperand &Op2 = MI->getOperand(2)
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopRerollPass.cpp | [all...] |
| Scalarizer.cpp | 391 Scatterer Op2 = scatter(&SI, SI.getOperand(2));
393 assert(Op2.size() == NumElems && "Mismatched select");
401 Res[I] = Builder.CreateSelect(Op0[I], Op1[I], Op2[I],
406 Res[I] = Builder.CreateSelect(Op0, Op1[I], Op2[I],
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 672 SDValue Op2 = Op.getOperand(2);
675 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
708 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
715 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
716 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
849 SDValue Op2 = Op.getOperand(2);
877 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
[all...] |
| LegalizeIntegerTypes.cpp | 185 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
189 Op2, N->getMemOperand(), N->getOrdering(),
220 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
223 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
226 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
[all...] |
| LegalizeVectorTypes.cpp | 145 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
147 Op0.getValueType(), Op0, Op1, Op2);
[all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.cpp | 602 unsigned Op1, Op2, NewDstIdx;
603 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
606 NewDstIdx = Op2;
607 else if (Op2 == UseOpIdx)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 172 ICToken Op2 = OperandStack.pop_back_val();
179 Val = Op1.second + Op2.second;
183 Val = Op1.second - Op2.second;
187 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
189 Val = Op1.second * Op2.second;
193 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
195 assert (Op2.second != 0 && "Division by zero!");
196 Val = Op1.second / Op2.second;
200 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
202 Val = Op1.second | Op2.second
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstructionCombining.cpp | [all...] |
| InstCombineCompares.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 119 unsigned Op2, bool Op2IsKill);
340 unsigned Op2, bool Op2IsKill) {
348 Op2 = constrainOperandRegClass(II, Op1, 3);
355 .addReg(Op2, Op2IsKill * RegState::Kill));
360 .addReg(Op2, Op2IsKill * RegState::Kill));
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
