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    Searched defs:Reg2 (Results 1 - 10 of 10) sorted by null

  /external/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64AsmBackend.cpp 415 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
426 Reg2 = getXRegFromWReg(Reg2);
428 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
431 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
434 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
437 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
440 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
445 Reg2 = getDRegFromBReg(Reg2);
    [all...]
  /external/llvm/lib/CodeGen/
TargetInstrInfo.cpp 138 unsigned Reg2 = MI->getOperand(Idx2).getReg();
149 Reg0 = Reg2;
151 } else if (HasDef && Reg0 == Reg2 &&
169 MI->getOperand(Idx1).setReg(Reg2);
  /external/llvm/lib/Target/AArch64/
AArch64FrameLowering.cpp 631 unsigned Reg2 = CSI[idx + 1].getReg();
653 assert(AArch64::GPR64RegClass.contains(Reg2) &&
661 assert(AArch64::FPR64RegClass.contains(Reg2) &&
671 << TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx()
682 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2))
706 unsigned Reg2 = CSI[i + 1].getReg();
724 assert(AArch64::GPR64RegClass.contains(Reg2) &&
731 assert(AArch64::FPR64RegClass.contains(Reg2) &&
740 << TRI->getName(Reg2) << ") -> fi#(" << CSI[i].getFrameIdx(
    [all...]
  /external/llvm/lib/Target/ARM/
Thumb2SizeReduction.cpp 645 unsigned Reg2 = MI->getOperand(2).getReg();
648 || !isARMLowRegister(Reg2))
650 if (Reg0 != Reg2) {
678 unsigned Reg2 = MI->getOperand(2).getReg();
679 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
    [all...]
ARMFastISel.cpp     [all...]
  /external/llvm/lib/MC/
MCDwarf.cpp     [all...]
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 252 unsigned Reg2 = MI->getOperand(2).getReg();
275 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
279 .addReg(Reg2, getKillRegState(Reg2IsKill))
286 MI->getOperand(0).setReg(Reg2);
290 MI->getOperand(1).setReg(Reg2);
    [all...]
  /external/llvm/utils/TableGen/
CodeGenRegisters.cpp     [all...]
  /external/llvm/lib/Target/Mips/
MipsISelLowering.cpp 598 // addiu $reg2, $reg1, y-1
605 // addiu $reg2, $reg1, y-1
    [all...]
  /external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp     [all...]

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