1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the TwoAddress instruction pass which is used 11 // by most register allocators. Two-Address instructions are rewritten 12 // from: 13 // 14 // A = B op C 15 // 16 // to: 17 // 18 // A = B 19 // A op= C 20 // 21 // Note that if a register allocator chooses to use this pass, that it 22 // has to be capable of handling the non-SSA nature of these rewritten 23 // virtual registers. 24 // 25 // It is also worth noting that the duplicate operand of the two 26 // address instruction is removed. 27 // 28 //===----------------------------------------------------------------------===// 29 30 #include "llvm/CodeGen/Passes.h" 31 #include "llvm/ADT/BitVector.h" 32 #include "llvm/ADT/DenseMap.h" 33 #include "llvm/ADT/STLExtras.h" 34 #include "llvm/ADT/SmallSet.h" 35 #include "llvm/ADT/Statistic.h" 36 #include "llvm/Analysis/AliasAnalysis.h" 37 #include "llvm/CodeGen/LiveIntervalAnalysis.h" 38 #include "llvm/CodeGen/LiveVariables.h" 39 #include "llvm/CodeGen/MachineFunctionPass.h" 40 #include "llvm/CodeGen/MachineInstr.h" 41 #include "llvm/CodeGen/MachineInstrBuilder.h" 42 #include "llvm/CodeGen/MachineRegisterInfo.h" 43 #include "llvm/IR/Function.h" 44 #include "llvm/MC/MCInstrItineraries.h" 45 #include "llvm/Support/CommandLine.h" 46 #include "llvm/Support/Debug.h" 47 #include "llvm/Support/ErrorHandling.h" 48 #include "llvm/Target/TargetInstrInfo.h" 49 #include "llvm/Target/TargetMachine.h" 50 #include "llvm/Target/TargetRegisterInfo.h" 51 using namespace llvm; 52 53 #define DEBUG_TYPE "twoaddrinstr" 54 55 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions"); 56 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce"); 57 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted"); 58 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address"); 59 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk"); 60 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up"); 61 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down"); 62 63 // Temporary flag to disable rescheduling. 64 static cl::opt<bool> 65 EnableRescheduling("twoaddr-reschedule", 66 cl::desc("Coalesce copies by rescheduling (default=true)"), 67 cl::init(true), cl::Hidden); 68 69 namespace { 70 class TwoAddressInstructionPass : public MachineFunctionPass { 71 MachineFunction *MF; 72 const TargetInstrInfo *TII; 73 const TargetRegisterInfo *TRI; 74 const InstrItineraryData *InstrItins; 75 MachineRegisterInfo *MRI; 76 LiveVariables *LV; 77 LiveIntervals *LIS; 78 AliasAnalysis *AA; 79 CodeGenOpt::Level OptLevel; 80 81 // The current basic block being processed. 82 MachineBasicBlock *MBB; 83 84 // DistanceMap - Keep track the distance of a MI from the start of the 85 // current basic block. 86 DenseMap<MachineInstr*, unsigned> DistanceMap; 87 88 // Set of already processed instructions in the current block. 89 SmallPtrSet<MachineInstr*, 8> Processed; 90 91 // SrcRegMap - A map from virtual registers to physical registers which are 92 // likely targets to be coalesced to due to copies from physical registers to 93 // virtual registers. e.g. v1024 = move r0. 94 DenseMap<unsigned, unsigned> SrcRegMap; 95 96 // DstRegMap - A map from virtual registers to physical registers which are 97 // likely targets to be coalesced to due to copies to physical registers from 98 // virtual registers. e.g. r1 = move v1024. 99 DenseMap<unsigned, unsigned> DstRegMap; 100 101 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg, 102 MachineBasicBlock::iterator OldPos); 103 104 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef); 105 106 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC, 107 MachineInstr *MI, unsigned Dist); 108 109 bool commuteInstruction(MachineBasicBlock::iterator &mi, 110 unsigned RegB, unsigned RegC, unsigned Dist); 111 112 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB); 113 114 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi, 115 MachineBasicBlock::iterator &nmi, 116 unsigned RegA, unsigned RegB, unsigned Dist); 117 118 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI); 119 120 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, 121 MachineBasicBlock::iterator &nmi, 122 unsigned Reg); 123 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi, 124 MachineBasicBlock::iterator &nmi, 125 unsigned Reg); 126 127 bool tryInstructionTransform(MachineBasicBlock::iterator &mi, 128 MachineBasicBlock::iterator &nmi, 129 unsigned SrcIdx, unsigned DstIdx, 130 unsigned Dist, bool shouldOnlyCommute); 131 132 void scanUses(unsigned DstReg); 133 134 void processCopy(MachineInstr *MI); 135 136 typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList; 137 typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap; 138 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&); 139 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist); 140 void eliminateRegSequence(MachineBasicBlock::iterator&); 141 142 public: 143 static char ID; // Pass identification, replacement for typeid 144 TwoAddressInstructionPass() : MachineFunctionPass(ID) { 145 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry()); 146 } 147 148 void getAnalysisUsage(AnalysisUsage &AU) const override { 149 AU.setPreservesCFG(); 150 AU.addRequired<AliasAnalysis>(); 151 AU.addPreserved<LiveVariables>(); 152 AU.addPreserved<SlotIndexes>(); 153 AU.addPreserved<LiveIntervals>(); 154 AU.addPreservedID(MachineLoopInfoID); 155 AU.addPreservedID(MachineDominatorsID); 156 MachineFunctionPass::getAnalysisUsage(AU); 157 } 158 159 /// runOnMachineFunction - Pass entry point. 160 bool runOnMachineFunction(MachineFunction&) override; 161 }; 162 } // end anonymous namespace 163 164 char TwoAddressInstructionPass::ID = 0; 165 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction", 166 "Two-Address instruction pass", false, false) 167 INITIALIZE_AG_DEPENDENCY(AliasAnalysis) 168 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction", 169 "Two-Address instruction pass", false, false) 170 171 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID; 172 173 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS); 174 175 /// sink3AddrInstruction - A two-address instruction has been converted to a 176 /// three-address instruction to avoid clobbering a register. Try to sink it 177 /// past the instruction that would kill the above mentioned register to reduce 178 /// register pressure. 179 bool TwoAddressInstructionPass:: 180 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg, 181 MachineBasicBlock::iterator OldPos) { 182 // FIXME: Shouldn't we be trying to do this before we three-addressify the 183 // instruction? After this transformation is done, we no longer need 184 // the instruction to be in three-address form. 185 186 // Check if it's safe to move this instruction. 187 bool SeenStore = true; // Be conservative. 188 if (!MI->isSafeToMove(TII, AA, SeenStore)) 189 return false; 190 191 unsigned DefReg = 0; 192 SmallSet<unsigned, 4> UseRegs; 193 194 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 195 const MachineOperand &MO = MI->getOperand(i); 196 if (!MO.isReg()) 197 continue; 198 unsigned MOReg = MO.getReg(); 199 if (!MOReg) 200 continue; 201 if (MO.isUse() && MOReg != SavedReg) 202 UseRegs.insert(MO.getReg()); 203 if (!MO.isDef()) 204 continue; 205 if (MO.isImplicit()) 206 // Don't try to move it if it implicitly defines a register. 207 return false; 208 if (DefReg) 209 // For now, don't move any instructions that define multiple registers. 210 return false; 211 DefReg = MO.getReg(); 212 } 213 214 // Find the instruction that kills SavedReg. 215 MachineInstr *KillMI = nullptr; 216 if (LIS) { 217 LiveInterval &LI = LIS->getInterval(SavedReg); 218 assert(LI.end() != LI.begin() && 219 "Reg should not have empty live interval."); 220 221 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot(); 222 LiveInterval::const_iterator I = LI.find(MBBEndIdx); 223 if (I != LI.end() && I->start < MBBEndIdx) 224 return false; 225 226 --I; 227 KillMI = LIS->getInstructionFromIndex(I->end); 228 } 229 if (!KillMI) { 230 for (MachineRegisterInfo::use_nodbg_iterator 231 UI = MRI->use_nodbg_begin(SavedReg), 232 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 233 MachineOperand &UseMO = *UI; 234 if (!UseMO.isKill()) 235 continue; 236 KillMI = UseMO.getParent(); 237 break; 238 } 239 } 240 241 // If we find the instruction that kills SavedReg, and it is in an 242 // appropriate location, we can try to sink the current instruction 243 // past it. 244 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI || 245 KillMI == OldPos || KillMI->isTerminator()) 246 return false; 247 248 // If any of the definitions are used by another instruction between the 249 // position and the kill use, then it's not safe to sink it. 250 // 251 // FIXME: This can be sped up if there is an easy way to query whether an 252 // instruction is before or after another instruction. Then we can use 253 // MachineRegisterInfo def / use instead. 254 MachineOperand *KillMO = nullptr; 255 MachineBasicBlock::iterator KillPos = KillMI; 256 ++KillPos; 257 258 unsigned NumVisited = 0; 259 for (MachineBasicBlock::iterator I = std::next(OldPos); I != KillPos; ++I) { 260 MachineInstr *OtherMI = I; 261 // DBG_VALUE cannot be counted against the limit. 262 if (OtherMI->isDebugValue()) 263 continue; 264 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost. 265 return false; 266 ++NumVisited; 267 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 268 MachineOperand &MO = OtherMI->getOperand(i); 269 if (!MO.isReg()) 270 continue; 271 unsigned MOReg = MO.getReg(); 272 if (!MOReg) 273 continue; 274 if (DefReg == MOReg) 275 return false; 276 277 if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) { 278 if (OtherMI == KillMI && MOReg == SavedReg) 279 // Save the operand that kills the register. We want to unset the kill 280 // marker if we can sink MI past it. 281 KillMO = &MO; 282 else if (UseRegs.count(MOReg)) 283 // One of the uses is killed before the destination. 284 return false; 285 } 286 } 287 } 288 assert(KillMO && "Didn't find kill"); 289 290 if (!LIS) { 291 // Update kill and LV information. 292 KillMO->setIsKill(false); 293 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); 294 KillMO->setIsKill(true); 295 296 if (LV) 297 LV->replaceKillInstruction(SavedReg, KillMI, MI); 298 } 299 300 // Move instruction to its destination. 301 MBB->remove(MI); 302 MBB->insert(KillPos, MI); 303 304 if (LIS) 305 LIS->handleMove(MI); 306 307 ++Num3AddrSunk; 308 return true; 309 } 310 311 /// noUseAfterLastDef - Return true if there are no intervening uses between the 312 /// last instruction in the MBB that defines the specified register and the 313 /// two-address instruction which is being processed. It also returns the last 314 /// def location by reference 315 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist, 316 unsigned &LastDef) { 317 LastDef = 0; 318 unsigned LastUse = Dist; 319 for (MachineOperand &MO : MRI->reg_operands(Reg)) { 320 MachineInstr *MI = MO.getParent(); 321 if (MI->getParent() != MBB || MI->isDebugValue()) 322 continue; 323 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 324 if (DI == DistanceMap.end()) 325 continue; 326 if (MO.isUse() && DI->second < LastUse) 327 LastUse = DI->second; 328 if (MO.isDef() && DI->second > LastDef) 329 LastDef = DI->second; 330 } 331 332 return !(LastUse > LastDef && LastUse < Dist); 333 } 334 335 /// isCopyToReg - Return true if the specified MI is a copy instruction or 336 /// a extract_subreg instruction. It also returns the source and destination 337 /// registers and whether they are physical registers by reference. 338 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, 339 unsigned &SrcReg, unsigned &DstReg, 340 bool &IsSrcPhys, bool &IsDstPhys) { 341 SrcReg = 0; 342 DstReg = 0; 343 if (MI.isCopy()) { 344 DstReg = MI.getOperand(0).getReg(); 345 SrcReg = MI.getOperand(1).getReg(); 346 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { 347 DstReg = MI.getOperand(0).getReg(); 348 SrcReg = MI.getOperand(2).getReg(); 349 } else 350 return false; 351 352 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); 353 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 354 return true; 355 } 356 357 /// isPLainlyKilled - Test if the given register value, which is used by the 358 // given instruction, is killed by the given instruction. 359 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, 360 LiveIntervals *LIS) { 361 if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) && 362 !LIS->isNotInMIMap(MI)) { 363 // FIXME: Sometimes tryInstructionTransform() will add instructions and 364 // test whether they can be folded before keeping them. In this case it 365 // sets a kill before recursively calling tryInstructionTransform() again. 366 // If there is no interval available, we assume that this instruction is 367 // one of those. A kill flag is manually inserted on the operand so the 368 // check below will handle it. 369 LiveInterval &LI = LIS->getInterval(Reg); 370 // This is to match the kill flag version where undefs don't have kill 371 // flags. 372 if (!LI.hasAtLeastOneValue()) 373 return false; 374 375 SlotIndex useIdx = LIS->getInstructionIndex(MI); 376 LiveInterval::const_iterator I = LI.find(useIdx); 377 assert(I != LI.end() && "Reg must be live-in to use."); 378 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx); 379 } 380 381 return MI->killsRegister(Reg); 382 } 383 384 /// isKilled - Test if the given register value, which is used by the given 385 /// instruction, is killed by the given instruction. This looks through 386 /// coalescable copies to see if the original value is potentially not killed. 387 /// 388 /// For example, in this code: 389 /// 390 /// %reg1034 = copy %reg1024 391 /// %reg1035 = copy %reg1025<kill> 392 /// %reg1036 = add %reg1034<kill>, %reg1035<kill> 393 /// 394 /// %reg1034 is not considered to be killed, since it is copied from a 395 /// register which is not killed. Treating it as not killed lets the 396 /// normal heuristics commute the (two-address) add, which lets 397 /// coalescing eliminate the extra copy. 398 /// 399 /// If allowFalsePositives is true then likely kills are treated as kills even 400 /// if it can't be proven that they are kills. 401 static bool isKilled(MachineInstr &MI, unsigned Reg, 402 const MachineRegisterInfo *MRI, 403 const TargetInstrInfo *TII, 404 LiveIntervals *LIS, 405 bool allowFalsePositives) { 406 MachineInstr *DefMI = &MI; 407 for (;;) { 408 // All uses of physical registers are likely to be kills. 409 if (TargetRegisterInfo::isPhysicalRegister(Reg) && 410 (allowFalsePositives || MRI->hasOneUse(Reg))) 411 return true; 412 if (!isPlainlyKilled(DefMI, Reg, LIS)) 413 return false; 414 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 415 return true; 416 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg); 417 // If there are multiple defs, we can't do a simple analysis, so just 418 // go with what the kill flag says. 419 if (std::next(Begin) != MRI->def_end()) 420 return true; 421 DefMI = Begin->getParent(); 422 bool IsSrcPhys, IsDstPhys; 423 unsigned SrcReg, DstReg; 424 // If the def is something other than a copy, then it isn't going to 425 // be coalesced, so follow the kill flag. 426 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 427 return true; 428 Reg = SrcReg; 429 } 430 } 431 432 /// isTwoAddrUse - Return true if the specified MI uses the specified register 433 /// as a two-address use. If so, return the destination register by reference. 434 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { 435 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) { 436 const MachineOperand &MO = MI.getOperand(i); 437 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 438 continue; 439 unsigned ti; 440 if (MI.isRegTiedToDefOperand(i, &ti)) { 441 DstReg = MI.getOperand(ti).getReg(); 442 return true; 443 } 444 } 445 return false; 446 } 447 448 /// findOnlyInterestingUse - Given a register, if has a single in-basic block 449 /// use, return the use instruction if it's a copy or a two-address use. 450 static 451 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, 452 MachineRegisterInfo *MRI, 453 const TargetInstrInfo *TII, 454 bool &IsCopy, 455 unsigned &DstReg, bool &IsDstPhys) { 456 if (!MRI->hasOneNonDBGUse(Reg)) 457 // None or more than one use. 458 return nullptr; 459 MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg); 460 if (UseMI.getParent() != MBB) 461 return nullptr; 462 unsigned SrcReg; 463 bool IsSrcPhys; 464 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { 465 IsCopy = true; 466 return &UseMI; 467 } 468 IsDstPhys = false; 469 if (isTwoAddrUse(UseMI, Reg, DstReg)) { 470 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 471 return &UseMI; 472 } 473 return nullptr; 474 } 475 476 /// getMappedReg - Return the physical register the specified virtual register 477 /// might be mapped to. 478 static unsigned 479 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) { 480 while (TargetRegisterInfo::isVirtualRegister(Reg)) { 481 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg); 482 if (SI == RegMap.end()) 483 return 0; 484 Reg = SI->second; 485 } 486 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 487 return Reg; 488 return 0; 489 } 490 491 /// regsAreCompatible - Return true if the two registers are equal or aliased. 492 /// 493 static bool 494 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { 495 if (RegA == RegB) 496 return true; 497 if (!RegA || !RegB) 498 return false; 499 return TRI->regsOverlap(RegA, RegB); 500 } 501 502 503 /// isProfitableToCommute - Return true if it's potentially profitable to commute 504 /// the two-address instruction that's being processed. 505 bool 506 TwoAddressInstructionPass:: 507 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC, 508 MachineInstr *MI, unsigned Dist) { 509 if (OptLevel == CodeGenOpt::None) 510 return false; 511 512 // Determine if it's profitable to commute this two address instruction. In 513 // general, we want no uses between this instruction and the definition of 514 // the two-address register. 515 // e.g. 516 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 517 // %reg1029<def> = MOV8rr %reg1028 518 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 519 // insert => %reg1030<def> = MOV8rr %reg1028 520 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 521 // In this case, it might not be possible to coalesce the second MOV8rr 522 // instruction if the first one is coalesced. So it would be profitable to 523 // commute it: 524 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 525 // %reg1029<def> = MOV8rr %reg1028 526 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 527 // insert => %reg1030<def> = MOV8rr %reg1029 528 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead> 529 530 if (!isPlainlyKilled(MI, regC, LIS)) 531 return false; 532 533 // Ok, we have something like: 534 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 535 // let's see if it's worth commuting it. 536 537 // Look for situations like this: 538 // %reg1024<def> = MOV r1 539 // %reg1025<def> = MOV r0 540 // %reg1026<def> = ADD %reg1024, %reg1025 541 // r0 = MOV %reg1026 542 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy. 543 unsigned ToRegA = getMappedReg(regA, DstRegMap); 544 if (ToRegA) { 545 unsigned FromRegB = getMappedReg(regB, SrcRegMap); 546 unsigned FromRegC = getMappedReg(regC, SrcRegMap); 547 bool BComp = !FromRegB || regsAreCompatible(FromRegB, ToRegA, TRI); 548 bool CComp = !FromRegC || regsAreCompatible(FromRegC, ToRegA, TRI); 549 if (BComp != CComp) 550 return !BComp && CComp; 551 } 552 553 // If there is a use of regC between its last def (could be livein) and this 554 // instruction, then bail. 555 unsigned LastDefC = 0; 556 if (!noUseAfterLastDef(regC, Dist, LastDefC)) 557 return false; 558 559 // If there is a use of regB between its last def (could be livein) and this 560 // instruction, then go ahead and make this transformation. 561 unsigned LastDefB = 0; 562 if (!noUseAfterLastDef(regB, Dist, LastDefB)) 563 return true; 564 565 // Since there are no intervening uses for both registers, then commute 566 // if the def of regC is closer. Its live interval is shorter. 567 return LastDefB && LastDefC && LastDefC > LastDefB; 568 } 569 570 /// commuteInstruction - Commute a two-address instruction and update the basic 571 /// block, distance map, and live variables if needed. Return true if it is 572 /// successful. 573 bool TwoAddressInstructionPass:: 574 commuteInstruction(MachineBasicBlock::iterator &mi, 575 unsigned RegB, unsigned RegC, unsigned Dist) { 576 MachineInstr *MI = mi; 577 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI); 578 MachineInstr *NewMI = TII->commuteInstruction(MI); 579 580 if (NewMI == nullptr) { 581 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n"); 582 return false; 583 } 584 585 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI); 586 assert(NewMI == MI && 587 "TargetInstrInfo::commuteInstruction() should not return a new " 588 "instruction unless it was requested."); 589 590 // Update source register map. 591 unsigned FromRegC = getMappedReg(RegC, SrcRegMap); 592 if (FromRegC) { 593 unsigned RegA = MI->getOperand(0).getReg(); 594 SrcRegMap[RegA] = FromRegC; 595 } 596 597 return true; 598 } 599 600 /// isProfitableToConv3Addr - Return true if it is profitable to convert the 601 /// given 2-address instruction to a 3-address one. 602 bool 603 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ 604 // Look for situations like this: 605 // %reg1024<def> = MOV r1 606 // %reg1025<def> = MOV r0 607 // %reg1026<def> = ADD %reg1024, %reg1025 608 // r2 = MOV %reg1026 609 // Turn ADD into a 3-address instruction to avoid a copy. 610 unsigned FromRegB = getMappedReg(RegB, SrcRegMap); 611 if (!FromRegB) 612 return false; 613 unsigned ToRegA = getMappedReg(RegA, DstRegMap); 614 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI)); 615 } 616 617 /// convertInstTo3Addr - Convert the specified two-address instruction into a 618 /// three address one. Return true if this transformation was successful. 619 bool 620 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi, 621 MachineBasicBlock::iterator &nmi, 622 unsigned RegA, unsigned RegB, 623 unsigned Dist) { 624 // FIXME: Why does convertToThreeAddress() need an iterator reference? 625 MachineFunction::iterator MFI = MBB; 626 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV); 627 assert(MBB == MFI && "convertToThreeAddress changed iterator reference"); 628 if (!NewMI) 629 return false; 630 631 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi); 632 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI); 633 bool Sunk = false; 634 635 if (LIS) 636 LIS->ReplaceMachineInstrInMaps(mi, NewMI); 637 638 if (NewMI->findRegisterUseOperand(RegB, false, TRI)) 639 // FIXME: Temporary workaround. If the new instruction doesn't 640 // uses RegB, convertToThreeAddress must have created more 641 // then one instruction. 642 Sunk = sink3AddrInstruction(NewMI, RegB, mi); 643 644 MBB->erase(mi); // Nuke the old inst. 645 646 if (!Sunk) { 647 DistanceMap.insert(std::make_pair(NewMI, Dist)); 648 mi = NewMI; 649 nmi = std::next(mi); 650 } 651 652 // Update source and destination register maps. 653 SrcRegMap.erase(RegA); 654 DstRegMap.erase(RegB); 655 return true; 656 } 657 658 /// scanUses - Scan forward recursively for only uses, update maps if the use 659 /// is a copy or a two-address instruction. 660 void 661 TwoAddressInstructionPass::scanUses(unsigned DstReg) { 662 SmallVector<unsigned, 4> VirtRegPairs; 663 bool IsDstPhys; 664 bool IsCopy = false; 665 unsigned NewReg = 0; 666 unsigned Reg = DstReg; 667 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy, 668 NewReg, IsDstPhys)) { 669 if (IsCopy && !Processed.insert(UseMI)) 670 break; 671 672 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 673 if (DI != DistanceMap.end()) 674 // Earlier in the same MBB.Reached via a back edge. 675 break; 676 677 if (IsDstPhys) { 678 VirtRegPairs.push_back(NewReg); 679 break; 680 } 681 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second; 682 if (!isNew) 683 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!"); 684 VirtRegPairs.push_back(NewReg); 685 Reg = NewReg; 686 } 687 688 if (!VirtRegPairs.empty()) { 689 unsigned ToReg = VirtRegPairs.back(); 690 VirtRegPairs.pop_back(); 691 while (!VirtRegPairs.empty()) { 692 unsigned FromReg = VirtRegPairs.back(); 693 VirtRegPairs.pop_back(); 694 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second; 695 if (!isNew) 696 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!"); 697 ToReg = FromReg; 698 } 699 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second; 700 if (!isNew) 701 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!"); 702 } 703 } 704 705 /// processCopy - If the specified instruction is not yet processed, process it 706 /// if it's a copy. For a copy instruction, we find the physical registers the 707 /// source and destination registers might be mapped to. These are kept in 708 /// point-to maps used to determine future optimizations. e.g. 709 /// v1024 = mov r0 710 /// v1025 = mov r1 711 /// v1026 = add v1024, v1025 712 /// r1 = mov r1026 713 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially 714 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is 715 /// potentially joined with r1 on the output side. It's worthwhile to commute 716 /// 'add' to eliminate a copy. 717 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) { 718 if (Processed.count(MI)) 719 return; 720 721 bool IsSrcPhys, IsDstPhys; 722 unsigned SrcReg, DstReg; 723 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 724 return; 725 726 if (IsDstPhys && !IsSrcPhys) 727 DstRegMap.insert(std::make_pair(SrcReg, DstReg)); 728 else if (!IsDstPhys && IsSrcPhys) { 729 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second; 730 if (!isNew) 731 assert(SrcRegMap[DstReg] == SrcReg && 732 "Can't map to two src physical registers!"); 733 734 scanUses(DstReg); 735 } 736 737 Processed.insert(MI); 738 return; 739 } 740 741 /// rescheduleMIBelowKill - If there is one more local instruction that reads 742 /// 'Reg' and it kills 'Reg, consider moving the instruction below the kill 743 /// instruction in order to eliminate the need for the copy. 744 bool TwoAddressInstructionPass:: 745 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, 746 MachineBasicBlock::iterator &nmi, 747 unsigned Reg) { 748 // Bail immediately if we don't have LV or LIS available. We use them to find 749 // kills efficiently. 750 if (!LV && !LIS) 751 return false; 752 753 MachineInstr *MI = &*mi; 754 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 755 if (DI == DistanceMap.end()) 756 // Must be created from unfolded load. Don't waste time trying this. 757 return false; 758 759 MachineInstr *KillMI = nullptr; 760 if (LIS) { 761 LiveInterval &LI = LIS->getInterval(Reg); 762 assert(LI.end() != LI.begin() && 763 "Reg should not have empty live interval."); 764 765 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot(); 766 LiveInterval::const_iterator I = LI.find(MBBEndIdx); 767 if (I != LI.end() && I->start < MBBEndIdx) 768 return false; 769 770 --I; 771 KillMI = LIS->getInstructionFromIndex(I->end); 772 } else { 773 KillMI = LV->getVarInfo(Reg).findKill(MBB); 774 } 775 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike()) 776 // Don't mess with copies, they may be coalesced later. 777 return false; 778 779 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() || 780 KillMI->isBranch() || KillMI->isTerminator()) 781 // Don't move pass calls, etc. 782 return false; 783 784 unsigned DstReg; 785 if (isTwoAddrUse(*KillMI, Reg, DstReg)) 786 return false; 787 788 bool SeenStore = true; 789 if (!MI->isSafeToMove(TII, AA, SeenStore)) 790 return false; 791 792 if (TII->getInstrLatency(InstrItins, MI) > 1) 793 // FIXME: Needs more sophisticated heuristics. 794 return false; 795 796 SmallSet<unsigned, 2> Uses; 797 SmallSet<unsigned, 2> Kills; 798 SmallSet<unsigned, 2> Defs; 799 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 800 const MachineOperand &MO = MI->getOperand(i); 801 if (!MO.isReg()) 802 continue; 803 unsigned MOReg = MO.getReg(); 804 if (!MOReg) 805 continue; 806 if (MO.isDef()) 807 Defs.insert(MOReg); 808 else { 809 Uses.insert(MOReg); 810 if (MOReg != Reg && (MO.isKill() || 811 (LIS && isPlainlyKilled(MI, MOReg, LIS)))) 812 Kills.insert(MOReg); 813 } 814 } 815 816 // Move the copies connected to MI down as well. 817 MachineBasicBlock::iterator Begin = MI; 818 MachineBasicBlock::iterator AfterMI = std::next(Begin); 819 820 MachineBasicBlock::iterator End = AfterMI; 821 while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) { 822 Defs.insert(End->getOperand(0).getReg()); 823 ++End; 824 } 825 826 // Check if the reschedule will not break depedencies. 827 unsigned NumVisited = 0; 828 MachineBasicBlock::iterator KillPos = KillMI; 829 ++KillPos; 830 for (MachineBasicBlock::iterator I = End; I != KillPos; ++I) { 831 MachineInstr *OtherMI = I; 832 // DBG_VALUE cannot be counted against the limit. 833 if (OtherMI->isDebugValue()) 834 continue; 835 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. 836 return false; 837 ++NumVisited; 838 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() || 839 OtherMI->isBranch() || OtherMI->isTerminator()) 840 // Don't move pass calls, etc. 841 return false; 842 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 843 const MachineOperand &MO = OtherMI->getOperand(i); 844 if (!MO.isReg()) 845 continue; 846 unsigned MOReg = MO.getReg(); 847 if (!MOReg) 848 continue; 849 if (MO.isDef()) { 850 if (Uses.count(MOReg)) 851 // Physical register use would be clobbered. 852 return false; 853 if (!MO.isDead() && Defs.count(MOReg)) 854 // May clobber a physical register def. 855 // FIXME: This may be too conservative. It's ok if the instruction 856 // is sunken completely below the use. 857 return false; 858 } else { 859 if (Defs.count(MOReg)) 860 return false; 861 bool isKill = MO.isKill() || 862 (LIS && isPlainlyKilled(OtherMI, MOReg, LIS)); 863 if (MOReg != Reg && 864 ((isKill && Uses.count(MOReg)) || Kills.count(MOReg))) 865 // Don't want to extend other live ranges and update kills. 866 return false; 867 if (MOReg == Reg && !isKill) 868 // We can't schedule across a use of the register in question. 869 return false; 870 // Ensure that if this is register in question, its the kill we expect. 871 assert((MOReg != Reg || OtherMI == KillMI) && 872 "Found multiple kills of a register in a basic block"); 873 } 874 } 875 } 876 877 // Move debug info as well. 878 while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue()) 879 --Begin; 880 881 nmi = End; 882 MachineBasicBlock::iterator InsertPos = KillPos; 883 if (LIS) { 884 // We have to move the copies first so that the MBB is still well-formed 885 // when calling handleMove(). 886 for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) { 887 MachineInstr *CopyMI = MBBI; 888 ++MBBI; 889 MBB->splice(InsertPos, MBB, CopyMI); 890 LIS->handleMove(CopyMI); 891 InsertPos = CopyMI; 892 } 893 End = std::next(MachineBasicBlock::iterator(MI)); 894 } 895 896 // Copies following MI may have been moved as well. 897 MBB->splice(InsertPos, MBB, Begin, End); 898 DistanceMap.erase(DI); 899 900 // Update live variables 901 if (LIS) { 902 LIS->handleMove(MI); 903 } else { 904 LV->removeVirtualRegisterKilled(Reg, KillMI); 905 LV->addVirtualRegisterKilled(Reg, MI); 906 } 907 908 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI); 909 return true; 910 } 911 912 /// isDefTooClose - Return true if the re-scheduling will put the given 913 /// instruction too close to the defs of its register dependencies. 914 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist, 915 MachineInstr *MI) { 916 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { 917 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike()) 918 continue; 919 if (&DefMI == MI) 920 return true; // MI is defining something KillMI uses 921 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI); 922 if (DDI == DistanceMap.end()) 923 return true; // Below MI 924 unsigned DefDist = DDI->second; 925 assert(Dist > DefDist && "Visited def already?"); 926 if (TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist)) 927 return true; 928 } 929 return false; 930 } 931 932 /// rescheduleKillAboveMI - If there is one more local instruction that reads 933 /// 'Reg' and it kills 'Reg, consider moving the kill instruction above the 934 /// current two-address instruction in order to eliminate the need for the 935 /// copy. 936 bool TwoAddressInstructionPass:: 937 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi, 938 MachineBasicBlock::iterator &nmi, 939 unsigned Reg) { 940 // Bail immediately if we don't have LV or LIS available. We use them to find 941 // kills efficiently. 942 if (!LV && !LIS) 943 return false; 944 945 MachineInstr *MI = &*mi; 946 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 947 if (DI == DistanceMap.end()) 948 // Must be created from unfolded load. Don't waste time trying this. 949 return false; 950 951 MachineInstr *KillMI = nullptr; 952 if (LIS) { 953 LiveInterval &LI = LIS->getInterval(Reg); 954 assert(LI.end() != LI.begin() && 955 "Reg should not have empty live interval."); 956 957 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot(); 958 LiveInterval::const_iterator I = LI.find(MBBEndIdx); 959 if (I != LI.end() && I->start < MBBEndIdx) 960 return false; 961 962 --I; 963 KillMI = LIS->getInstructionFromIndex(I->end); 964 } else { 965 KillMI = LV->getVarInfo(Reg).findKill(MBB); 966 } 967 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike()) 968 // Don't mess with copies, they may be coalesced later. 969 return false; 970 971 unsigned DstReg; 972 if (isTwoAddrUse(*KillMI, Reg, DstReg)) 973 return false; 974 975 bool SeenStore = true; 976 if (!KillMI->isSafeToMove(TII, AA, SeenStore)) 977 return false; 978 979 SmallSet<unsigned, 2> Uses; 980 SmallSet<unsigned, 2> Kills; 981 SmallSet<unsigned, 2> Defs; 982 SmallSet<unsigned, 2> LiveDefs; 983 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) { 984 const MachineOperand &MO = KillMI->getOperand(i); 985 if (!MO.isReg()) 986 continue; 987 unsigned MOReg = MO.getReg(); 988 if (MO.isUse()) { 989 if (!MOReg) 990 continue; 991 if (isDefTooClose(MOReg, DI->second, MI)) 992 return false; 993 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS)); 994 if (MOReg == Reg && !isKill) 995 return false; 996 Uses.insert(MOReg); 997 if (isKill && MOReg != Reg) 998 Kills.insert(MOReg); 999 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) { 1000 Defs.insert(MOReg); 1001 if (!MO.isDead()) 1002 LiveDefs.insert(MOReg); 1003 } 1004 } 1005 1006 // Check if the reschedule will not break depedencies. 1007 unsigned NumVisited = 0; 1008 MachineBasicBlock::iterator KillPos = KillMI; 1009 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) { 1010 MachineInstr *OtherMI = I; 1011 // DBG_VALUE cannot be counted against the limit. 1012 if (OtherMI->isDebugValue()) 1013 continue; 1014 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. 1015 return false; 1016 ++NumVisited; 1017 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() || 1018 OtherMI->isBranch() || OtherMI->isTerminator()) 1019 // Don't move pass calls, etc. 1020 return false; 1021 SmallVector<unsigned, 2> OtherDefs; 1022 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 1023 const MachineOperand &MO = OtherMI->getOperand(i); 1024 if (!MO.isReg()) 1025 continue; 1026 unsigned MOReg = MO.getReg(); 1027 if (!MOReg) 1028 continue; 1029 if (MO.isUse()) { 1030 if (Defs.count(MOReg)) 1031 // Moving KillMI can clobber the physical register if the def has 1032 // not been seen. 1033 return false; 1034 if (Kills.count(MOReg)) 1035 // Don't want to extend other live ranges and update kills. 1036 return false; 1037 if (OtherMI != MI && MOReg == Reg && 1038 !(MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS)))) 1039 // We can't schedule across a use of the register in question. 1040 return false; 1041 } else { 1042 OtherDefs.push_back(MOReg); 1043 } 1044 } 1045 1046 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) { 1047 unsigned MOReg = OtherDefs[i]; 1048 if (Uses.count(MOReg)) 1049 return false; 1050 if (TargetRegisterInfo::isPhysicalRegister(MOReg) && 1051 LiveDefs.count(MOReg)) 1052 return false; 1053 // Physical register def is seen. 1054 Defs.erase(MOReg); 1055 } 1056 } 1057 1058 // Move the old kill above MI, don't forget to move debug info as well. 1059 MachineBasicBlock::iterator InsertPos = mi; 1060 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue()) 1061 --InsertPos; 1062 MachineBasicBlock::iterator From = KillMI; 1063 MachineBasicBlock::iterator To = std::next(From); 1064 while (std::prev(From)->isDebugValue()) 1065 --From; 1066 MBB->splice(InsertPos, MBB, From, To); 1067 1068 nmi = std::prev(InsertPos); // Backtrack so we process the moved instr. 1069 DistanceMap.erase(DI); 1070 1071 // Update live variables 1072 if (LIS) { 1073 LIS->handleMove(KillMI); 1074 } else { 1075 LV->removeVirtualRegisterKilled(Reg, KillMI); 1076 LV->addVirtualRegisterKilled(Reg, MI); 1077 } 1078 1079 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI); 1080 return true; 1081 } 1082 1083 /// tryInstructionTransform - For the case where an instruction has a single 1084 /// pair of tied register operands, attempt some transformations that may 1085 /// either eliminate the tied operands or improve the opportunities for 1086 /// coalescing away the register copy. Returns true if no copy needs to be 1087 /// inserted to untie mi's operands (either because they were untied, or 1088 /// because mi was rescheduled, and will be visited again later). If the 1089 /// shouldOnlyCommute flag is true, only instruction commutation is attempted. 1090 bool TwoAddressInstructionPass:: 1091 tryInstructionTransform(MachineBasicBlock::iterator &mi, 1092 MachineBasicBlock::iterator &nmi, 1093 unsigned SrcIdx, unsigned DstIdx, 1094 unsigned Dist, bool shouldOnlyCommute) { 1095 if (OptLevel == CodeGenOpt::None) 1096 return false; 1097 1098 MachineInstr &MI = *mi; 1099 unsigned regA = MI.getOperand(DstIdx).getReg(); 1100 unsigned regB = MI.getOperand(SrcIdx).getReg(); 1101 1102 assert(TargetRegisterInfo::isVirtualRegister(regB) && 1103 "cannot make instruction into two-address form"); 1104 bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true); 1105 1106 if (TargetRegisterInfo::isVirtualRegister(regA)) 1107 scanUses(regA); 1108 1109 // Check if it is profitable to commute the operands. 1110 unsigned SrcOp1, SrcOp2; 1111 unsigned regC = 0; 1112 unsigned regCIdx = ~0U; 1113 bool TryCommute = false; 1114 bool AggressiveCommute = false; 1115 if (MI.isCommutable() && MI.getNumOperands() >= 3 && 1116 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) { 1117 if (SrcIdx == SrcOp1) 1118 regCIdx = SrcOp2; 1119 else if (SrcIdx == SrcOp2) 1120 regCIdx = SrcOp1; 1121 1122 if (regCIdx != ~0U) { 1123 regC = MI.getOperand(regCIdx).getReg(); 1124 if (!regBKilled && isKilled(MI, regC, MRI, TII, LIS, false)) 1125 // If C dies but B does not, swap the B and C operands. 1126 // This makes the live ranges of A and C joinable. 1127 TryCommute = true; 1128 else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) { 1129 TryCommute = true; 1130 AggressiveCommute = true; 1131 } 1132 } 1133 } 1134 1135 // If it's profitable to commute, try to do so. 1136 if (TryCommute && commuteInstruction(mi, regB, regC, Dist)) { 1137 ++NumCommuted; 1138 if (AggressiveCommute) 1139 ++NumAggrCommuted; 1140 return false; 1141 } 1142 1143 if (shouldOnlyCommute) 1144 return false; 1145 1146 // If there is one more use of regB later in the same MBB, consider 1147 // re-schedule this MI below it. 1148 if (EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) { 1149 ++NumReSchedDowns; 1150 return true; 1151 } 1152 1153 if (MI.isConvertibleTo3Addr()) { 1154 // This instruction is potentially convertible to a true 1155 // three-address instruction. Check if it is profitable. 1156 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { 1157 // Try to convert it. 1158 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) { 1159 ++NumConvertedTo3Addr; 1160 return true; // Done with this instruction. 1161 } 1162 } 1163 } 1164 1165 // If there is one more use of regB later in the same MBB, consider 1166 // re-schedule it before this MI if it's legal. 1167 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) { 1168 ++NumReSchedUps; 1169 return true; 1170 } 1171 1172 // If this is an instruction with a load folded into it, try unfolding 1173 // the load, e.g. avoid this: 1174 // movq %rdx, %rcx 1175 // addq (%rax), %rcx 1176 // in favor of this: 1177 // movq (%rax), %rcx 1178 // addq %rdx, %rcx 1179 // because it's preferable to schedule a load than a register copy. 1180 if (MI.mayLoad() && !regBKilled) { 1181 // Determine if a load can be unfolded. 1182 unsigned LoadRegIndex; 1183 unsigned NewOpc = 1184 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), 1185 /*UnfoldLoad=*/true, 1186 /*UnfoldStore=*/false, 1187 &LoadRegIndex); 1188 if (NewOpc != 0) { 1189 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc); 1190 if (UnfoldMCID.getNumDefs() == 1) { 1191 // Unfold the load. 1192 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI); 1193 const TargetRegisterClass *RC = 1194 TRI->getAllocatableClass( 1195 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF)); 1196 unsigned Reg = MRI->createVirtualRegister(RC); 1197 SmallVector<MachineInstr *, 2> NewMIs; 1198 if (!TII->unfoldMemoryOperand(*MF, &MI, Reg, 1199 /*UnfoldLoad=*/true,/*UnfoldStore=*/false, 1200 NewMIs)) { 1201 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); 1202 return false; 1203 } 1204 assert(NewMIs.size() == 2 && 1205 "Unfolded a load into multiple instructions!"); 1206 // The load was previously folded, so this is the only use. 1207 NewMIs[1]->addRegisterKilled(Reg, TRI); 1208 1209 // Tentatively insert the instructions into the block so that they 1210 // look "normal" to the transformation logic. 1211 MBB->insert(mi, NewMIs[0]); 1212 MBB->insert(mi, NewMIs[1]); 1213 1214 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] 1215 << "2addr: NEW INST: " << *NewMIs[1]); 1216 1217 // Transform the instruction, now that it no longer has a load. 1218 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); 1219 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); 1220 MachineBasicBlock::iterator NewMI = NewMIs[1]; 1221 bool TransformResult = 1222 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true); 1223 (void)TransformResult; 1224 assert(!TransformResult && 1225 "tryInstructionTransform() should return false."); 1226 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) { 1227 // Success, or at least we made an improvement. Keep the unfolded 1228 // instructions and discard the original. 1229 if (LV) { 1230 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1231 MachineOperand &MO = MI.getOperand(i); 1232 if (MO.isReg() && 1233 TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 1234 if (MO.isUse()) { 1235 if (MO.isKill()) { 1236 if (NewMIs[0]->killsRegister(MO.getReg())) 1237 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]); 1238 else { 1239 assert(NewMIs[1]->killsRegister(MO.getReg()) && 1240 "Kill missing after load unfold!"); 1241 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]); 1242 } 1243 } 1244 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) { 1245 if (NewMIs[1]->registerDefIsDead(MO.getReg())) 1246 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]); 1247 else { 1248 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) && 1249 "Dead flag missing after load unfold!"); 1250 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]); 1251 } 1252 } 1253 } 1254 } 1255 LV->addVirtualRegisterKilled(Reg, NewMIs[1]); 1256 } 1257 1258 SmallVector<unsigned, 4> OrigRegs; 1259 if (LIS) { 1260 for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(), 1261 MOE = MI.operands_end(); MOI != MOE; ++MOI) { 1262 if (MOI->isReg()) 1263 OrigRegs.push_back(MOI->getReg()); 1264 } 1265 } 1266 1267 MI.eraseFromParent(); 1268 1269 // Update LiveIntervals. 1270 if (LIS) { 1271 MachineBasicBlock::iterator Begin(NewMIs[0]); 1272 MachineBasicBlock::iterator End(NewMIs[1]); 1273 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs); 1274 } 1275 1276 mi = NewMIs[1]; 1277 } else { 1278 // Transforming didn't eliminate the tie and didn't lead to an 1279 // improvement. Clean up the unfolded instructions and keep the 1280 // original. 1281 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); 1282 NewMIs[0]->eraseFromParent(); 1283 NewMIs[1]->eraseFromParent(); 1284 } 1285 } 1286 } 1287 } 1288 1289 return false; 1290 } 1291 1292 // Collect tied operands of MI that need to be handled. 1293 // Rewrite trivial cases immediately. 1294 // Return true if any tied operands where found, including the trivial ones. 1295 bool TwoAddressInstructionPass:: 1296 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) { 1297 const MCInstrDesc &MCID = MI->getDesc(); 1298 bool AnyOps = false; 1299 unsigned NumOps = MI->getNumOperands(); 1300 1301 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { 1302 unsigned DstIdx = 0; 1303 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) 1304 continue; 1305 AnyOps = true; 1306 MachineOperand &SrcMO = MI->getOperand(SrcIdx); 1307 MachineOperand &DstMO = MI->getOperand(DstIdx); 1308 unsigned SrcReg = SrcMO.getReg(); 1309 unsigned DstReg = DstMO.getReg(); 1310 // Tied constraint already satisfied? 1311 if (SrcReg == DstReg) 1312 continue; 1313 1314 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); 1315 1316 // Deal with <undef> uses immediately - simply rewrite the src operand. 1317 if (SrcMO.isUndef() && !DstMO.getSubReg()) { 1318 // Constrain the DstReg register class if required. 1319 if (TargetRegisterInfo::isVirtualRegister(DstReg)) 1320 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx, 1321 TRI, *MF)) 1322 MRI->constrainRegClass(DstReg, RC); 1323 SrcMO.setReg(DstReg); 1324 SrcMO.setSubReg(0); 1325 DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI); 1326 continue; 1327 } 1328 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); 1329 } 1330 return AnyOps; 1331 } 1332 1333 // Process a list of tied MI operands that all use the same source register. 1334 // The tied pairs are of the form (SrcIdx, DstIdx). 1335 void 1336 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI, 1337 TiedPairList &TiedPairs, 1338 unsigned &Dist) { 1339 bool IsEarlyClobber = false; 1340 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) { 1341 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second); 1342 IsEarlyClobber |= DstMO.isEarlyClobber(); 1343 } 1344 1345 bool RemovedKillFlag = false; 1346 bool AllUsesCopied = true; 1347 unsigned LastCopiedReg = 0; 1348 SlotIndex LastCopyIdx; 1349 unsigned RegB = 0; 1350 unsigned SubRegB = 0; 1351 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) { 1352 unsigned SrcIdx = TiedPairs[tpi].first; 1353 unsigned DstIdx = TiedPairs[tpi].second; 1354 1355 const MachineOperand &DstMO = MI->getOperand(DstIdx); 1356 unsigned RegA = DstMO.getReg(); 1357 1358 // Grab RegB from the instruction because it may have changed if the 1359 // instruction was commuted. 1360 RegB = MI->getOperand(SrcIdx).getReg(); 1361 SubRegB = MI->getOperand(SrcIdx).getSubReg(); 1362 1363 if (RegA == RegB) { 1364 // The register is tied to multiple destinations (or else we would 1365 // not have continued this far), but this use of the register 1366 // already matches the tied destination. Leave it. 1367 AllUsesCopied = false; 1368 continue; 1369 } 1370 LastCopiedReg = RegA; 1371 1372 assert(TargetRegisterInfo::isVirtualRegister(RegB) && 1373 "cannot make instruction into two-address form"); 1374 1375 #ifndef NDEBUG 1376 // First, verify that we don't have a use of "a" in the instruction 1377 // (a = b + a for example) because our transformation will not 1378 // work. This should never occur because we are in SSA form. 1379 for (unsigned i = 0; i != MI->getNumOperands(); ++i) 1380 assert(i == DstIdx || 1381 !MI->getOperand(i).isReg() || 1382 MI->getOperand(i).getReg() != RegA); 1383 #endif 1384 1385 // Emit a copy. 1386 MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1387 TII->get(TargetOpcode::COPY), RegA); 1388 // If this operand is folding a truncation, the truncation now moves to the 1389 // copy so that the register classes remain valid for the operands. 1390 MIB.addReg(RegB, 0, SubRegB); 1391 const TargetRegisterClass *RC = MRI->getRegClass(RegB); 1392 if (SubRegB) { 1393 if (TargetRegisterInfo::isVirtualRegister(RegA)) { 1394 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA), 1395 SubRegB) && 1396 "tied subregister must be a truncation"); 1397 // The superreg class will not be used to constrain the subreg class. 1398 RC = nullptr; 1399 } 1400 else { 1401 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB)) 1402 && "tied subregister must be a truncation"); 1403 } 1404 } 1405 1406 // Update DistanceMap. 1407 MachineBasicBlock::iterator PrevMI = MI; 1408 --PrevMI; 1409 DistanceMap.insert(std::make_pair(PrevMI, Dist)); 1410 DistanceMap[MI] = ++Dist; 1411 1412 if (LIS) { 1413 LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).getRegSlot(); 1414 1415 if (TargetRegisterInfo::isVirtualRegister(RegA)) { 1416 LiveInterval &LI = LIS->getInterval(RegA); 1417 VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator()); 1418 SlotIndex endIdx = 1419 LIS->getInstructionIndex(MI).getRegSlot(IsEarlyClobber); 1420 LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI)); 1421 } 1422 } 1423 1424 DEBUG(dbgs() << "\t\tprepend:\t" << *MIB); 1425 1426 MachineOperand &MO = MI->getOperand(SrcIdx); 1427 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && 1428 "inconsistent operand info for 2-reg pass"); 1429 if (MO.isKill()) { 1430 MO.setIsKill(false); 1431 RemovedKillFlag = true; 1432 } 1433 1434 // Make sure regA is a legal regclass for the SrcIdx operand. 1435 if (TargetRegisterInfo::isVirtualRegister(RegA) && 1436 TargetRegisterInfo::isVirtualRegister(RegB)) 1437 MRI->constrainRegClass(RegA, RC); 1438 MO.setReg(RegA); 1439 // The getMatchingSuper asserts guarantee that the register class projected 1440 // by SubRegB is compatible with RegA with no subregister. So regardless of 1441 // whether the dest oper writes a subreg, the source oper should not. 1442 MO.setSubReg(0); 1443 1444 // Propagate SrcRegMap. 1445 SrcRegMap[RegA] = RegB; 1446 } 1447 1448 1449 if (AllUsesCopied) { 1450 if (!IsEarlyClobber) { 1451 // Replace other (un-tied) uses of regB with LastCopiedReg. 1452 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1453 MachineOperand &MO = MI->getOperand(i); 1454 if (MO.isReg() && MO.getReg() == RegB && MO.getSubReg() == SubRegB && 1455 MO.isUse()) { 1456 if (MO.isKill()) { 1457 MO.setIsKill(false); 1458 RemovedKillFlag = true; 1459 } 1460 MO.setReg(LastCopiedReg); 1461 MO.setSubReg(0); 1462 } 1463 } 1464 } 1465 1466 // Update live variables for regB. 1467 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) { 1468 MachineBasicBlock::iterator PrevMI = MI; 1469 --PrevMI; 1470 LV->addVirtualRegisterKilled(RegB, PrevMI); 1471 } 1472 1473 // Update LiveIntervals. 1474 if (LIS) { 1475 LiveInterval &LI = LIS->getInterval(RegB); 1476 SlotIndex MIIdx = LIS->getInstructionIndex(MI); 1477 LiveInterval::const_iterator I = LI.find(MIIdx); 1478 assert(I != LI.end() && "RegB must be live-in to use."); 1479 1480 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber); 1481 if (I->end == UseIdx) 1482 LI.removeSegment(LastCopyIdx, UseIdx); 1483 } 1484 1485 } else if (RemovedKillFlag) { 1486 // Some tied uses of regB matched their destination registers, so 1487 // regB is still used in this instruction, but a kill flag was 1488 // removed from a different tied use of regB, so now we need to add 1489 // a kill flag to one of the remaining uses of regB. 1490 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1491 MachineOperand &MO = MI->getOperand(i); 1492 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { 1493 MO.setIsKill(true); 1494 break; 1495 } 1496 } 1497 } 1498 } 1499 1500 /// runOnMachineFunction - Reduce two-address instructions to two operands. 1501 /// 1502 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) { 1503 MF = &Func; 1504 const TargetMachine &TM = MF->getTarget(); 1505 MRI = &MF->getRegInfo(); 1506 TII = TM.getInstrInfo(); 1507 TRI = TM.getRegisterInfo(); 1508 InstrItins = TM.getInstrItineraryData(); 1509 LV = getAnalysisIfAvailable<LiveVariables>(); 1510 LIS = getAnalysisIfAvailable<LiveIntervals>(); 1511 AA = &getAnalysis<AliasAnalysis>(); 1512 OptLevel = TM.getOptLevel(); 1513 1514 bool MadeChange = false; 1515 1516 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n"); 1517 DEBUG(dbgs() << "********** Function: " 1518 << MF->getName() << '\n'); 1519 1520 // This pass takes the function out of SSA form. 1521 MRI->leaveSSA(); 1522 1523 TiedOperandMap TiedOperands; 1524 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end(); 1525 MBBI != MBBE; ++MBBI) { 1526 MBB = MBBI; 1527 unsigned Dist = 0; 1528 DistanceMap.clear(); 1529 SrcRegMap.clear(); 1530 DstRegMap.clear(); 1531 Processed.clear(); 1532 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end(); 1533 mi != me; ) { 1534 MachineBasicBlock::iterator nmi = std::next(mi); 1535 if (mi->isDebugValue()) { 1536 mi = nmi; 1537 continue; 1538 } 1539 1540 // Expand REG_SEQUENCE instructions. This will position mi at the first 1541 // expanded instruction. 1542 if (mi->isRegSequence()) 1543 eliminateRegSequence(mi); 1544 1545 DistanceMap.insert(std::make_pair(mi, ++Dist)); 1546 1547 processCopy(&*mi); 1548 1549 // First scan through all the tied register uses in this instruction 1550 // and record a list of pairs of tied operands for each register. 1551 if (!collectTiedOperands(mi, TiedOperands)) { 1552 mi = nmi; 1553 continue; 1554 } 1555 1556 ++NumTwoAddressInstrs; 1557 MadeChange = true; 1558 DEBUG(dbgs() << '\t' << *mi); 1559 1560 // If the instruction has a single pair of tied operands, try some 1561 // transformations that may either eliminate the tied operands or 1562 // improve the opportunities for coalescing away the register copy. 1563 if (TiedOperands.size() == 1) { 1564 SmallVectorImpl<std::pair<unsigned, unsigned> > &TiedPairs 1565 = TiedOperands.begin()->second; 1566 if (TiedPairs.size() == 1) { 1567 unsigned SrcIdx = TiedPairs[0].first; 1568 unsigned DstIdx = TiedPairs[0].second; 1569 unsigned SrcReg = mi->getOperand(SrcIdx).getReg(); 1570 unsigned DstReg = mi->getOperand(DstIdx).getReg(); 1571 if (SrcReg != DstReg && 1572 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) { 1573 // The tied operands have been eliminated or shifted further down the 1574 // block to ease elimination. Continue processing with 'nmi'. 1575 TiedOperands.clear(); 1576 mi = nmi; 1577 continue; 1578 } 1579 } 1580 } 1581 1582 // Now iterate over the information collected above. 1583 for (TiedOperandMap::iterator OI = TiedOperands.begin(), 1584 OE = TiedOperands.end(); OI != OE; ++OI) { 1585 processTiedPairs(mi, OI->second, Dist); 1586 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi); 1587 } 1588 1589 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form. 1590 if (mi->isInsertSubreg()) { 1591 // From %reg = INSERT_SUBREG %reg, %subreg, subidx 1592 // To %reg:subidx = COPY %subreg 1593 unsigned SubIdx = mi->getOperand(3).getImm(); 1594 mi->RemoveOperand(3); 1595 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx"); 1596 mi->getOperand(0).setSubReg(SubIdx); 1597 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef()); 1598 mi->RemoveOperand(1); 1599 mi->setDesc(TII->get(TargetOpcode::COPY)); 1600 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi); 1601 } 1602 1603 // Clear TiedOperands here instead of at the top of the loop 1604 // since most instructions do not have tied operands. 1605 TiedOperands.clear(); 1606 mi = nmi; 1607 } 1608 } 1609 1610 if (LIS) 1611 MF->verify(this, "After two-address instruction pass"); 1612 1613 return MadeChange; 1614 } 1615 1616 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process. 1617 /// 1618 /// The instruction is turned into a sequence of sub-register copies: 1619 /// 1620 /// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1 1621 /// 1622 /// Becomes: 1623 /// 1624 /// %dst:ssub0<def,undef> = COPY %v1 1625 /// %dst:ssub1<def> = COPY %v2 1626 /// 1627 void TwoAddressInstructionPass:: 1628 eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { 1629 MachineInstr *MI = MBBI; 1630 unsigned DstReg = MI->getOperand(0).getReg(); 1631 if (MI->getOperand(0).getSubReg() || 1632 TargetRegisterInfo::isPhysicalRegister(DstReg) || 1633 !(MI->getNumOperands() & 1)) { 1634 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); 1635 llvm_unreachable(nullptr); 1636 } 1637 1638 SmallVector<unsigned, 4> OrigRegs; 1639 if (LIS) { 1640 OrigRegs.push_back(MI->getOperand(0).getReg()); 1641 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) 1642 OrigRegs.push_back(MI->getOperand(i).getReg()); 1643 } 1644 1645 bool DefEmitted = false; 1646 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { 1647 MachineOperand &UseMO = MI->getOperand(i); 1648 unsigned SrcReg = UseMO.getReg(); 1649 unsigned SubIdx = MI->getOperand(i+1).getImm(); 1650 // Nothing needs to be inserted for <undef> operands. 1651 if (UseMO.isUndef()) 1652 continue; 1653 1654 // Defer any kill flag to the last operand using SrcReg. Otherwise, we 1655 // might insert a COPY that uses SrcReg after is was killed. 1656 bool isKill = UseMO.isKill(); 1657 if (isKill) 1658 for (unsigned j = i + 2; j < e; j += 2) 1659 if (MI->getOperand(j).getReg() == SrcReg) { 1660 MI->getOperand(j).setIsKill(); 1661 UseMO.setIsKill(false); 1662 isKill = false; 1663 break; 1664 } 1665 1666 // Insert the sub-register copy. 1667 MachineInstr *CopyMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1668 TII->get(TargetOpcode::COPY)) 1669 .addReg(DstReg, RegState::Define, SubIdx) 1670 .addOperand(UseMO); 1671 1672 // The first def needs an <undef> flag because there is no live register 1673 // before it. 1674 if (!DefEmitted) { 1675 CopyMI->getOperand(0).setIsUndef(true); 1676 // Return an iterator pointing to the first inserted instr. 1677 MBBI = CopyMI; 1678 } 1679 DefEmitted = true; 1680 1681 // Update LiveVariables' kill info. 1682 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg)) 1683 LV->replaceKillInstruction(SrcReg, MI, CopyMI); 1684 1685 DEBUG(dbgs() << "Inserted: " << *CopyMI); 1686 } 1687 1688 MachineBasicBlock::iterator EndMBBI = 1689 std::next(MachineBasicBlock::iterator(MI)); 1690 1691 if (!DefEmitted) { 1692 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF"); 1693 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); 1694 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j) 1695 MI->RemoveOperand(j); 1696 } else { 1697 DEBUG(dbgs() << "Eliminated: " << *MI); 1698 MI->eraseFromParent(); 1699 } 1700 1701 // Udpate LiveIntervals. 1702 if (LIS) 1703 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs); 1704 } 1705
