| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
99 addOffset(const MachineInstrBuilder &MIB, int Offset) {
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
108 addRegOffset(const MachineInstrBuilder &MIB,
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
115 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
123 addFullAddress(const MachineInstrBuilder &MIB,
128 MIB.addReg(AM.Base.Reg)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 25 /// Add a BDX memory reference for frame object FI to MIB.
27 addFrameReference(const MachineInstrBuilder &MIB, int FI) {
28 MachineInstr *MI = MIB;
43 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO);
|
| SystemZFrameLowering.cpp | 105 // Add GPR64 to the save instruction being built by MIB, which is in basic
109 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
115 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
174 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
177 addSavedGPR(MBB, MIB, LowGPR, false);
178 addSavedGPR(MBB, MIB, HighGPR, false);
181 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
188 addSavedGPR(MBB, MIB, Reg, true);
194 addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
244 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG))
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 207 MachineInstrBuilder &MIB,
240 MIB.addReg(VRBase, RegState::Define);
253 MIB.addReg(VRBase, RegState::Define);
265 MIB.addReg(VRBase, RegState::Define);
307 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
320 const MCInstrDesc &MCID = MIB->getDesc();
352 unsigned Idx = MIB->getNumOperands();
354 MIB->getOperand(Idx-1).isReg() &&
355 MIB->getOperand(Idx-1).isImplicit())
362 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill)
[all...] |
| InstrEmitter.h | 53 MachineInstrBuilder &MIB,
66 void AddRegisterOperand(MachineInstrBuilder &MIB,
77 void AddOperand(MachineInstrBuilder &MIB,
|
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 389 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
397 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
399 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
401 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
403 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
406 MIB.addOperand(MI.getOperand(OpIdx++));
409 MIB.addOperand(MI.getOperand(OpIdx++));
410 MIB.addOperand(MI.getOperand(OpIdx++));
413 MIB.addOperand(MI.getOperand(OpIdx++));
423 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| ARMInstrInfo.cpp | 128 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
132 MIB.addImm(0);
133 AddDefaultPred(MIB);
139 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
143 AddDefaultPred(MIB);
|
| Thumb2SizeReduction.cpp | 494 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
496 MIB.addOperand(MI->getOperand(0));
497 MIB.addOperand(MI->getOperand(1));
500 MIB.addImm(OffsetImm / Scale);
505 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
510 MIB.addOperand(MI->getOperand(OpNum));
513 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
516 MIB.setMIFlags(MI->getFlags());
518 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
554 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc()
[all...] |
| Thumb1RegisterInfo.cpp | 128 MachineInstrBuilder MIB =
131 MIB = AddDefaultT1CC(MIB);
133 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
135 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
136 AddDefaultPred(MIB);
240 const MachineInstrBuilder MIB =
243 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
259 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
261 MIB = AddDefaultT1CC(MIB)
[all...] |
| Thumb2InstrInfo.cpp | 157 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
159 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
160 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
161 AddDefaultPred(MIB);
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
201 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
202 AddDefaultPred(MIB);
[all...] |
| ARMBaseInstrInfo.cpp | 691 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
692 MIB.addReg(SrcReg, getKillRegState(KillSrc));
694 MIB.addReg(SrcReg, getKillRegState(KillSrc));
695 AddDefaultPred(MIB);
784 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
788 return MIB.addReg(Reg, State);
791 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
792 return MIB.addReg(Reg, State, SubIdx);
832 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
833 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI)
[all...] |
| Thumb1FrameLowering.cpp | 400 MachineInstrBuilder MIB =
403 AddDefaultPred(MIB);
404 MIB.copyImplicitOps(&*MBBI);
424 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
425 AddDefaultPred(MIB);
443 MIB.addReg(Reg, getKillRegState(isKill));
445 MIB.setMIFlags(MachineInstr::FrameSetup);
463 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
464 AddDefaultPred(MIB);
474 (*MIB).setDesc(TII.get(ARM::tPOP_RET))
[all...] |
| ARMBaseInstrInfo.h | 136 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
327 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
328 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
332 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
333 return MIB.addReg(0);
337 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
339 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
343 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
344 return MIB.addReg(0);
|
| ARMFastISel.cpp | 217 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
219 const MachineInstrBuilder &MIB,
265 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
266 MachineInstr *MI = &*MIB;
272 AddDefaultPred(MIB);
279 AddDefaultT1CC(MIB);
281 AddDefaultCC(MIB);
283 return MIB;
631 MachineInstrBuilder MIB;
634 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)
[all...] |
| MLxExpansionPass.cpp | 293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
297 MIB.addImm(LaneImm);
298 MIB.addImm(Pred).addReg(PredReg);
300 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
305 MIB.addReg(TmpReg, getKillRegState(true))
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
310 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2ITBlockPass.cpp | 183 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
191 MachineBasicBlock::iterator InsertPos = MIB;
239 MIB.addImm(Mask);
|
| ARMLoadStoreOptimizer.cpp | 515 MachineInstrBuilder MIB;
522 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode));
525 MIB.addReg(Base, getDefRegState(true))
535 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode));
536 MIB.addReg(Base, getKillRegState(BaseKill));
539 MIB.addImm(Pred).addReg(PredReg);
542 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
547 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 103 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
107 MIB.addReg(Cond[i].getReg());
109 MIB.addImm(Cond[i].getImm());
113 MIB.addMBB(TBB);
287 MachineInstrBuilder MIB;
288 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
291 MIB.addOperand(I->getOperand(J));
293 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
294 return MIB;
|
| Mips16InstrInfo.cpp | 87 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
90 MIB.addReg(DestReg, RegState::Define);
93 MIB.addReg(SrcReg, getKillRegState(KillSrc));
173 static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
186 MIB.addReg(Reg, Flags);
205 MachineInstrBuilder MIB;
207 MIB = BuildMI(MBB, I, DL, get(Opc));
209 addSaveRestoreRegs(MIB, CSI);
211 MIB.addReg(Mips::S2);
213 MIB.addImm(FrameSize)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 97 MachineInstrBuilder MIB =
114 transferImpOps(MI, MIB, MIB1);
164 MachineInstrBuilder MIB =
195 transferImpOps(MI, MIB, MIB1);
216 transferImpOps(MI, MIB, MIB2);
347 MachineInstrBuilder MIB =
369 transferImpOps(MI, MIB, MIB1);
383 transferImpOps(MI, MIB, MIB2);
402 MachineInstrBuilder MIB =
407 transferImpOps(MI, MIB, MIB)
[all...] |
| AArch64AdvSIMDScalarPass.cpp | 266 MachineInstrBuilder MIB =
270 DEBUG(dbgs() << " adding copy: " << *MIB);
272 return MIB;
|
| AArch64BranchRelaxation.cpp | 430 MachineInstrBuilder MIB = BuildMI(
435 MIB.addOperand(MI->getOperand(1));
437 invertBccCondition(MIB);
438 MIB.addMBB(NextBB);
|
| AArch64LoadStoreOptimizer.cpp | 311 MachineInstrBuilder MIB = BuildMI(*I->getParent(), InsertionPoint,
317 (void)MIB;
327 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
539 MachineInstrBuilder MIB =
545 (void)MIB;
553 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
582 MachineInstrBuilder MIB =
588 (void)MIB;
596 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 110 MachineInstrBuilder MIB = BuildMI(*MBB.getParent(), FirstMI->getDebugLoc(),
112 Bundle.prepend(MIB);
191 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
|
