| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 168 MachineInstr *DefMI = nullptr, *UseMI = nullptr;
180 if (UseMI && UseMI != MI)
185 UseMI = MI;
188 if (!DefMI || !UseMI)
195 LIS.getInstructionIndex(UseMI)))
199 // Assume there are stores between DefMI and UseMI.
205 << " into single use: " << *UseMI);
208 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
211 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI)
[all...] |
| RegisterScavenging.cpp | 282 /// longest after StargMII. UseMI is set to the instruction where the search
290 MachineBasicBlock::iterator &UseMI) {
348 UseMI = RestorePointMI;
387 MachineBasicBlock::iterator UseMI;
388 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
413 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
425 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
427 II = std::prev(UseMI);
433 Scavenged[SI].Restore = std::prev(UseMI);
|
| MachineRegisterInfo.cpp | 428 MachineInstr *UseMI = &*I;
429 if (UseMI->isDebugValue())
430 UseMI->getOperand(0).setReg(0U);
|
| MachineSSAUpdater.cpp | 223 MachineInstr *UseMI = U.getParent();
225 if (UseMI->isPHI()) {
226 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U);
229 NewVR = GetValueInMiddleOfBlock(UseMI->getParent());
|
| LiveIntervalAnalysis.cpp | 334 MachineInstr *UseMI = &*(I++);
335 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
337 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
344 DEBUG(dbgs() << Idx << '\t' << *UseMI
[all...] |
| PeepholeOptimizer.cpp | 306 MachineInstr *UseMI = UseMO.getParent();
307 if (UseMI == MI)
310 if (UseMI->isPHI()) {
336 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
339 MachineBasicBlock *UseMBB = UseMI->getParent();
342 if (!LocalMIs.count(UseMI))
380 MachineInstr *UseMI = UseMO->getParent();
381 MachineBasicBlock *UseMBB = UseMI->getParent();
392 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc()
[all...] |
| RegAllocFast.cpp | 594 const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg);
596 if (UseMI.isCopyLike())
597 Hint = UseMI.getOperand(0).getReg();
[all...] |
| TailDuplication.cpp | 270 MachineInstr *UseMI = UseMO.getParent();
272 if (UseMI->isDebugValue()) {
277 UseMI->eraseFromParent();
280 if (UseMI->getParent() == DefBB && !UseMI->isPHI())
345 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
346 if (UseMI.isDebugValue())
348 if (UseMI.getParent() != BB)
[all...] |
| RegisterCoalescer.cpp | 625 MachineInstr *UseMI = MO.getParent();
626 unsigned OpNo = &MO - &UseMI->getOperand(0);
627 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
632 if (UseMI->isRegTiedToDefOperand(OpNo))
671 MachineInstr *UseMI = UseMO.getParent();
673 if (UseMI->isDebugValue()) {
679 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
689 if (UseMI == CopyMI)
691 if (!UseMI->isCopy())
693 if (UseMI->getOperand(0).getReg() != IntB.reg |
[all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 124 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg);
125 if (UseMI->getParent() != MBB)
128 while (UseMI->isCopy() || UseMI->isInsertSubreg()) {
129 Reg = UseMI->getOperand(0).getReg();
133 UseMI = &*MRI->use_instr_nodbg_begin(Reg);
134 if (UseMI->getParent() != MBB)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | 509 MachineInstr *UseMI = &*(UI++);
510 if (UseMI->isDebugValue()) continue;
511 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
512 CopyUseMI = UseMI; continue;
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 926 MachineInstr *UseMI = Use.getParent();
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 110 const MachineInstr *UseMI,
113 UseMI, UseIdx);
130 if (UseMI->isBranch() && IsRegCR) {
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | [all...] |
