1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SelectionDAG::LegalizeVectors method. 11 // 12 // The vector legalizer looks for vector operations which might need to be 13 // scalarized and legalizes them. This is a separate step from Legalize because 14 // scalarizing can introduce illegal types. For example, suppose we have an 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition 16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the 17 // operation, which introduces nodes with the illegal type i64 which must be 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 19 // the operation must be unrolled, which introduces nodes with the illegal 20 // type i8 which must be promoted. 21 // 22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR, 23 // or operations that happen to take a vector which are custom-lowered; 24 // the legalization for such operations never produces nodes 25 // with illegal types, so it's okay to put off legalizing them until 26 // SelectionDAG::Legalize runs. 27 // 28 //===----------------------------------------------------------------------===// 29 30 #include "llvm/CodeGen/SelectionDAG.h" 31 #include "llvm/Target/TargetLowering.h" 32 using namespace llvm; 33 34 namespace { 35 class VectorLegalizer { 36 SelectionDAG& DAG; 37 const TargetLowering &TLI; 38 bool Changed; // Keep track of whether anything changed 39 40 /// For nodes that are of legal width, and that have more than one use, this 41 /// map indicates what regularized operand to use. This allows us to avoid 42 /// legalizing the same thing more than once. 43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes; 44 45 /// \brief Adds a node to the translation cache. 46 void AddLegalizedOperand(SDValue From, SDValue To) { 47 LegalizedNodes.insert(std::make_pair(From, To)); 48 // If someone requests legalization of the new node, return itself. 49 if (From != To) 50 LegalizedNodes.insert(std::make_pair(To, To)); 51 } 52 53 /// \brief Legalizes the given node. 54 SDValue LegalizeOp(SDValue Op); 55 56 /// \brief Assuming the node is legal, "legalize" the results. 57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result); 58 59 /// \brief Implements unrolling a VSETCC. 60 SDValue UnrollVSETCC(SDValue Op); 61 62 /// \brief Implement expand-based legalization of vector operations. 63 /// 64 /// This is just a high-level routine to dispatch to specific code paths for 65 /// operations to legalize them. 66 SDValue Expand(SDValue Op); 67 68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if 69 /// FSUB isn't legal. 70 /// 71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if 72 /// SINT_TO_FLOAT and SHR on vectors isn't legal. 73 SDValue ExpandUINT_TO_FLOAT(SDValue Op); 74 75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA. 76 SDValue ExpandSEXTINREG(SDValue Op); 77 78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG. 79 /// 80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper 81 /// type. The contents of the bits in the extended part of each element are 82 /// undef. 83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op); 84 85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG. 86 /// 87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper 88 /// type, then shifts left and arithmetic shifts right to introduce a sign 89 /// extension. 90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op); 91 92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG. 93 /// 94 /// Shuffles the low lanes of the operand into place and blends zeros into 95 /// the remaining lanes, finally bitcasting to the proper type. 96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op); 97 98 /// \brief Expand bswap of vectors into a shuffle if legal. 99 SDValue ExpandBSWAP(SDValue Op); 100 101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not 102 /// supported by the target. 103 SDValue ExpandVSELECT(SDValue Op); 104 SDValue ExpandSELECT(SDValue Op); 105 SDValue ExpandLoad(SDValue Op); 106 SDValue ExpandStore(SDValue Op); 107 SDValue ExpandFNEG(SDValue Op); 108 109 /// \brief Implements vector promotion. 110 /// 111 /// This is essentially just bitcasting the operands to a different type and 112 /// bitcasting the result back to the original type. 113 SDValue Promote(SDValue Op); 114 115 /// \brief Implements [SU]INT_TO_FP vector promotion. 116 /// 117 /// This is a [zs]ext of the input operand to the next size up. 118 SDValue PromoteINT_TO_FP(SDValue Op); 119 120 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type. 121 /// 122 /// It is promoted to the next size up integer type. The result is then 123 /// truncated back to the original type. 124 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned); 125 126 public: 127 /// \brief Begin legalizer the vector operations in the DAG. 128 bool Run(); 129 VectorLegalizer(SelectionDAG& dag) : 130 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} 131 }; 132 133 bool VectorLegalizer::Run() { 134 // Before we start legalizing vector nodes, check if there are any vectors. 135 bool HasVectors = false; 136 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 137 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) { 138 // Check if the values of the nodes contain vectors. We don't need to check 139 // the operands because we are going to check their values at some point. 140 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end(); 141 J != E; ++J) 142 HasVectors |= J->isVector(); 143 144 // If we found a vector node we can start the legalization. 145 if (HasVectors) 146 break; 147 } 148 149 // If this basic block has no vectors then no need to legalize vectors. 150 if (!HasVectors) 151 return false; 152 153 // The legalize process is inherently a bottom-up recursive process (users 154 // legalize their uses before themselves). Given infinite stack space, we 155 // could just start legalizing on the root and traverse the whole graph. In 156 // practice however, this causes us to run out of stack space on large basic 157 // blocks. To avoid this problem, compute an ordering of the nodes where each 158 // node is only legalized after all of its operands are legalized. 159 DAG.AssignTopologicalOrder(); 160 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 161 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) 162 LegalizeOp(SDValue(I, 0)); 163 164 // Finally, it's possible the root changed. Get the new root. 165 SDValue OldRoot = DAG.getRoot(); 166 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 167 DAG.setRoot(LegalizedNodes[OldRoot]); 168 169 LegalizedNodes.clear(); 170 171 // Remove dead nodes now. 172 DAG.RemoveDeadNodes(); 173 174 return Changed; 175 } 176 177 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) { 178 // Generic legalization: just pass the operand through. 179 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) 180 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 181 return Result.getValue(Op.getResNo()); 182 } 183 184 SDValue VectorLegalizer::LegalizeOp(SDValue Op) { 185 // Note that LegalizeOp may be reentered even from single-use nodes, which 186 // means that we always must cache transformed nodes. 187 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 188 if (I != LegalizedNodes.end()) return I->second; 189 190 SDNode* Node = Op.getNode(); 191 192 // Legalize the operands 193 SmallVector<SDValue, 8> Ops; 194 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 195 Ops.push_back(LegalizeOp(Node->getOperand(i))); 196 197 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0); 198 199 if (Op.getOpcode() == ISD::LOAD) { 200 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); 201 ISD::LoadExtType ExtType = LD->getExtensionType(); 202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { 203 if (TLI.isLoadExtLegal(LD->getExtensionType(), LD->getMemoryVT())) 204 return TranslateLegalizeResults(Op, Result); 205 Changed = true; 206 return LegalizeOp(ExpandLoad(Op)); 207 } 208 } else if (Op.getOpcode() == ISD::STORE) { 209 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode()); 210 EVT StVT = ST->getMemoryVT(); 211 MVT ValVT = ST->getValue().getSimpleValueType(); 212 if (StVT.isVector() && ST->isTruncatingStore()) 213 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) { 214 default: llvm_unreachable("This action is not supported yet!"); 215 case TargetLowering::Legal: 216 return TranslateLegalizeResults(Op, Result); 217 case TargetLowering::Custom: 218 Changed = true; 219 return TranslateLegalizeResults(Op, TLI.LowerOperation(Result, DAG)); 220 case TargetLowering::Expand: 221 Changed = true; 222 return LegalizeOp(ExpandStore(Op)); 223 } 224 } 225 226 bool HasVectorValue = false; 227 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end(); 228 J != E; 229 ++J) 230 HasVectorValue |= J->isVector(); 231 if (!HasVectorValue) 232 return TranslateLegalizeResults(Op, Result); 233 234 EVT QueryType; 235 switch (Op.getOpcode()) { 236 default: 237 return TranslateLegalizeResults(Op, Result); 238 case ISD::ADD: 239 case ISD::SUB: 240 case ISD::MUL: 241 case ISD::SDIV: 242 case ISD::UDIV: 243 case ISD::SREM: 244 case ISD::UREM: 245 case ISD::FADD: 246 case ISD::FSUB: 247 case ISD::FMUL: 248 case ISD::FDIV: 249 case ISD::FREM: 250 case ISD::AND: 251 case ISD::OR: 252 case ISD::XOR: 253 case ISD::SHL: 254 case ISD::SRA: 255 case ISD::SRL: 256 case ISD::ROTL: 257 case ISD::ROTR: 258 case ISD::BSWAP: 259 case ISD::CTLZ: 260 case ISD::CTTZ: 261 case ISD::CTLZ_ZERO_UNDEF: 262 case ISD::CTTZ_ZERO_UNDEF: 263 case ISD::CTPOP: 264 case ISD::SELECT: 265 case ISD::VSELECT: 266 case ISD::SELECT_CC: 267 case ISD::SETCC: 268 case ISD::ZERO_EXTEND: 269 case ISD::ANY_EXTEND: 270 case ISD::TRUNCATE: 271 case ISD::SIGN_EXTEND: 272 case ISD::FP_TO_SINT: 273 case ISD::FP_TO_UINT: 274 case ISD::FNEG: 275 case ISD::FABS: 276 case ISD::FCOPYSIGN: 277 case ISD::FSQRT: 278 case ISD::FSIN: 279 case ISD::FCOS: 280 case ISD::FPOWI: 281 case ISD::FPOW: 282 case ISD::FLOG: 283 case ISD::FLOG2: 284 case ISD::FLOG10: 285 case ISD::FEXP: 286 case ISD::FEXP2: 287 case ISD::FCEIL: 288 case ISD::FTRUNC: 289 case ISD::FRINT: 290 case ISD::FNEARBYINT: 291 case ISD::FROUND: 292 case ISD::FFLOOR: 293 case ISD::FP_ROUND: 294 case ISD::FP_EXTEND: 295 case ISD::FMA: 296 case ISD::SIGN_EXTEND_INREG: 297 case ISD::ANY_EXTEND_VECTOR_INREG: 298 case ISD::SIGN_EXTEND_VECTOR_INREG: 299 case ISD::ZERO_EXTEND_VECTOR_INREG: 300 QueryType = Node->getValueType(0); 301 break; 302 case ISD::FP_ROUND_INREG: 303 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 304 break; 305 case ISD::SINT_TO_FP: 306 case ISD::UINT_TO_FP: 307 QueryType = Node->getOperand(0).getValueType(); 308 break; 309 } 310 311 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) { 312 case TargetLowering::Promote: 313 Result = Promote(Op); 314 Changed = true; 315 break; 316 case TargetLowering::Legal: 317 break; 318 case TargetLowering::Custom: { 319 SDValue Tmp1 = TLI.LowerOperation(Op, DAG); 320 if (Tmp1.getNode()) { 321 Result = Tmp1; 322 break; 323 } 324 // FALL THROUGH 325 } 326 case TargetLowering::Expand: 327 Result = Expand(Op); 328 } 329 330 // Make sure that the generated code is itself legal. 331 if (Result != Op) { 332 Result = LegalizeOp(Result); 333 Changed = true; 334 } 335 336 // Note that LegalizeOp may be reentered even from single-use nodes, which 337 // means that we always must cache transformed nodes. 338 AddLegalizedOperand(Op, Result); 339 return Result; 340 } 341 342 SDValue VectorLegalizer::Promote(SDValue Op) { 343 // For a few operations there is a specific concept for promotion based on 344 // the operand's type. 345 switch (Op.getOpcode()) { 346 case ISD::SINT_TO_FP: 347 case ISD::UINT_TO_FP: 348 // "Promote" the operation by extending the operand. 349 return PromoteINT_TO_FP(Op); 350 case ISD::FP_TO_UINT: 351 case ISD::FP_TO_SINT: 352 // Promote the operation by extending the operand. 353 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT); 354 } 355 356 // The rest of the time, vector "promotion" is basically just bitcasting and 357 // doing the operation in a different type. For example, x86 promotes 358 // ISD::AND on v2i32 to v1i64. 359 MVT VT = Op.getSimpleValueType(); 360 assert(Op.getNode()->getNumValues() == 1 && 361 "Can't promote a vector with multiple results!"); 362 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); 363 SDLoc dl(Op); 364 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 365 366 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 367 if (Op.getOperand(j).getValueType().isVector()) 368 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); 369 else 370 Operands[j] = Op.getOperand(j); 371 } 372 373 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands); 374 375 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 376 } 377 378 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) { 379 // INT_TO_FP operations may require the input operand be promoted even 380 // when the type is otherwise legal. 381 EVT VT = Op.getOperand(0).getValueType(); 382 assert(Op.getNode()->getNumValues() == 1 && 383 "Can't promote a vector with multiple results!"); 384 385 // Normal getTypeToPromoteTo() doesn't work here, as that will promote 386 // by widening the vector w/ the same element width and twice the number 387 // of elements. We want the other way around, the same number of elements, 388 // each twice the width. 389 // 390 // Increase the bitwidth of the element to the next pow-of-two 391 // (which is greater than 8 bits). 392 393 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext()); 394 assert(NVT.isSimple() && "Promoting to a non-simple vector type!"); 395 SDLoc dl(Op); 396 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 397 398 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : 399 ISD::SIGN_EXTEND; 400 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 401 if (Op.getOperand(j).getValueType().isVector()) 402 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j)); 403 else 404 Operands[j] = Op.getOperand(j); 405 } 406 407 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands); 408 } 409 410 // For FP_TO_INT we promote the result type to a vector type with wider 411 // elements and then truncate the result. This is different from the default 412 // PromoteVector which uses bitcast to promote thus assumning that the 413 // promoted vector type has the same overall size. 414 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) { 415 assert(Op.getNode()->getNumValues() == 1 && 416 "Can't promote a vector with multiple results!"); 417 EVT VT = Op.getValueType(); 418 419 EVT NewVT; 420 unsigned NewOpc; 421 while (1) { 422 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext()); 423 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!"); 424 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) { 425 NewOpc = ISD::FP_TO_SINT; 426 break; 427 } 428 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) { 429 NewOpc = ISD::FP_TO_UINT; 430 break; 431 } 432 } 433 434 SDLoc loc(Op); 435 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0)); 436 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted); 437 } 438 439 440 SDValue VectorLegalizer::ExpandLoad(SDValue Op) { 441 SDLoc dl(Op); 442 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); 443 SDValue Chain = LD->getChain(); 444 SDValue BasePTR = LD->getBasePtr(); 445 EVT SrcVT = LD->getMemoryVT(); 446 ISD::LoadExtType ExtType = LD->getExtensionType(); 447 448 SmallVector<SDValue, 8> Vals; 449 SmallVector<SDValue, 8> LoadChains; 450 unsigned NumElem = SrcVT.getVectorNumElements(); 451 452 EVT SrcEltVT = SrcVT.getScalarType(); 453 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType(); 454 455 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) { 456 // When elements in a vector is not byte-addressable, we cannot directly 457 // load each element by advancing pointer, which could only address bytes. 458 // Instead, we load all significant words, mask bits off, and concatenate 459 // them to form each element. Finally, they are extended to destination 460 // scalar type to build the destination vector. 461 EVT WideVT = TLI.getPointerTy(); 462 463 assert(WideVT.isRound() && 464 "Could not handle the sophisticated case when the widest integer is" 465 " not power of 2."); 466 assert(WideVT.bitsGE(SrcEltVT) && 467 "Type is not legalized?"); 468 469 unsigned WideBytes = WideVT.getStoreSize(); 470 unsigned Offset = 0; 471 unsigned RemainingBytes = SrcVT.getStoreSize(); 472 SmallVector<SDValue, 8> LoadVals; 473 474 while (RemainingBytes > 0) { 475 SDValue ScalarLoad; 476 unsigned LoadBytes = WideBytes; 477 478 if (RemainingBytes >= LoadBytes) { 479 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR, 480 LD->getPointerInfo().getWithOffset(Offset), 481 LD->isVolatile(), LD->isNonTemporal(), 482 LD->isInvariant(), LD->getAlignment(), 483 LD->getTBAAInfo()); 484 } else { 485 EVT LoadVT = WideVT; 486 while (RemainingBytes < LoadBytes) { 487 LoadBytes >>= 1; // Reduce the load size by half. 488 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3); 489 } 490 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR, 491 LD->getPointerInfo().getWithOffset(Offset), 492 LoadVT, LD->isVolatile(), 493 LD->isNonTemporal(), LD->getAlignment(), 494 LD->getTBAAInfo()); 495 } 496 497 RemainingBytes -= LoadBytes; 498 Offset += LoadBytes; 499 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, 500 DAG.getConstant(LoadBytes, BasePTR.getValueType())); 501 502 LoadVals.push_back(ScalarLoad.getValue(0)); 503 LoadChains.push_back(ScalarLoad.getValue(1)); 504 } 505 506 // Extract bits, pack and extend/trunc them into destination type. 507 unsigned SrcEltBits = SrcEltVT.getSizeInBits(); 508 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT); 509 510 unsigned BitOffset = 0; 511 unsigned WideIdx = 0; 512 unsigned WideBits = WideVT.getSizeInBits(); 513 514 for (unsigned Idx = 0; Idx != NumElem; ++Idx) { 515 SDValue Lo, Hi, ShAmt; 516 517 if (BitOffset < WideBits) { 518 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT)); 519 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); 520 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask); 521 } 522 523 BitOffset += SrcEltBits; 524 if (BitOffset >= WideBits) { 525 WideIdx++; 526 Offset -= WideBits; 527 if (Offset > 0) { 528 ShAmt = DAG.getConstant(SrcEltBits - Offset, 529 TLI.getShiftAmountTy(WideVT)); 530 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt); 531 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask); 532 } 533 } 534 535 if (Hi.getNode()) 536 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi); 537 538 switch (ExtType) { 539 default: llvm_unreachable("Unknown extended-load op!"); 540 case ISD::EXTLOAD: 541 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT); 542 break; 543 case ISD::ZEXTLOAD: 544 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT); 545 break; 546 case ISD::SEXTLOAD: 547 ShAmt = DAG.getConstant(WideBits - SrcEltBits, 548 TLI.getShiftAmountTy(WideVT)); 549 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt); 550 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt); 551 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT); 552 break; 553 } 554 Vals.push_back(Lo); 555 } 556 } else { 557 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8; 558 559 for (unsigned Idx=0; Idx<NumElem; Idx++) { 560 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl, 561 Op.getNode()->getValueType(0).getScalarType(), 562 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride), 563 SrcVT.getScalarType(), 564 LD->isVolatile(), LD->isNonTemporal(), 565 LD->getAlignment(), LD->getTBAAInfo()); 566 567 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, 568 DAG.getConstant(Stride, BasePTR.getValueType())); 569 570 Vals.push_back(ScalarLoad.getValue(0)); 571 LoadChains.push_back(ScalarLoad.getValue(1)); 572 } 573 } 574 575 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); 576 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, 577 Op.getNode()->getValueType(0), Vals); 578 579 AddLegalizedOperand(Op.getValue(0), Value); 580 AddLegalizedOperand(Op.getValue(1), NewChain); 581 582 return (Op.getResNo() ? NewChain : Value); 583 } 584 585 SDValue VectorLegalizer::ExpandStore(SDValue Op) { 586 SDLoc dl(Op); 587 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode()); 588 SDValue Chain = ST->getChain(); 589 SDValue BasePTR = ST->getBasePtr(); 590 SDValue Value = ST->getValue(); 591 EVT StVT = ST->getMemoryVT(); 592 593 unsigned Alignment = ST->getAlignment(); 594 bool isVolatile = ST->isVolatile(); 595 bool isNonTemporal = ST->isNonTemporal(); 596 const MDNode *TBAAInfo = ST->getTBAAInfo(); 597 598 unsigned NumElem = StVT.getVectorNumElements(); 599 // The type of the data we want to save 600 EVT RegVT = Value.getValueType(); 601 EVT RegSclVT = RegVT.getScalarType(); 602 // The type of data as saved in memory. 603 EVT MemSclVT = StVT.getScalarType(); 604 605 // Cast floats into integers 606 unsigned ScalarSize = MemSclVT.getSizeInBits(); 607 608 // Round odd types to the next pow of two. 609 if (!isPowerOf2_32(ScalarSize)) 610 ScalarSize = NextPowerOf2(ScalarSize); 611 612 // Store Stride in bytes 613 unsigned Stride = ScalarSize/8; 614 // Extract each of the elements from the original vector 615 // and save them into memory individually. 616 SmallVector<SDValue, 8> Stores; 617 for (unsigned Idx = 0; Idx < NumElem; Idx++) { 618 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 619 RegSclVT, Value, DAG.getConstant(Idx, TLI.getVectorIdxTy())); 620 621 // This scalar TruncStore may be illegal, but we legalize it later. 622 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR, 623 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT, 624 isVolatile, isNonTemporal, Alignment, TBAAInfo); 625 626 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, 627 DAG.getConstant(Stride, BasePTR.getValueType())); 628 629 Stores.push_back(Store); 630 } 631 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); 632 AddLegalizedOperand(Op, TF); 633 return TF; 634 } 635 636 SDValue VectorLegalizer::Expand(SDValue Op) { 637 switch (Op->getOpcode()) { 638 case ISD::SIGN_EXTEND_INREG: 639 return ExpandSEXTINREG(Op); 640 case ISD::ANY_EXTEND_VECTOR_INREG: 641 return ExpandANY_EXTEND_VECTOR_INREG(Op); 642 case ISD::SIGN_EXTEND_VECTOR_INREG: 643 return ExpandSIGN_EXTEND_VECTOR_INREG(Op); 644 case ISD::ZERO_EXTEND_VECTOR_INREG: 645 return ExpandZERO_EXTEND_VECTOR_INREG(Op); 646 case ISD::BSWAP: 647 return ExpandBSWAP(Op); 648 case ISD::VSELECT: 649 return ExpandVSELECT(Op); 650 case ISD::SELECT: 651 return ExpandSELECT(Op); 652 case ISD::UINT_TO_FP: 653 return ExpandUINT_TO_FLOAT(Op); 654 case ISD::FNEG: 655 return ExpandFNEG(Op); 656 case ISD::SETCC: 657 return UnrollVSETCC(Op); 658 default: 659 return DAG.UnrollVectorOp(Op.getNode()); 660 } 661 } 662 663 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) { 664 // Lower a select instruction where the condition is a scalar and the 665 // operands are vectors. Lower this select to VSELECT and implement it 666 // using XOR AND OR. The selector bit is broadcasted. 667 EVT VT = Op.getValueType(); 668 SDLoc DL(Op); 669 670 SDValue Mask = Op.getOperand(0); 671 SDValue Op1 = Op.getOperand(1); 672 SDValue Op2 = Op.getOperand(2); 673 674 assert(VT.isVector() && !Mask.getValueType().isVector() 675 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 676 677 unsigned NumElem = VT.getVectorNumElements(); 678 679 // If we can't even use the basic vector operations of 680 // AND,OR,XOR, we will have to scalarize the op. 681 // Notice that the operation may be 'promoted' which means that it is 682 // 'bitcasted' to another type which is handled. 683 // Also, we need to be able to construct a splat vector using BUILD_VECTOR. 684 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand || 685 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand || 686 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand || 687 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand) 688 return DAG.UnrollVectorOp(Op.getNode()); 689 690 // Generate a mask operand. 691 EVT MaskTy = VT.changeVectorElementTypeToInteger(); 692 693 // What is the size of each element in the vector mask. 694 EVT BitTy = MaskTy.getScalarType(); 695 696 Mask = DAG.getSelect(DL, BitTy, Mask, 697 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy), 698 DAG.getConstant(0, BitTy)); 699 700 // Broadcast the mask so that the entire vector is all-one or all zero. 701 SmallVector<SDValue, 8> Ops(NumElem, Mask); 702 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops); 703 704 // Bitcast the operands to be the same type as the mask. 705 // This is needed when we select between FP types because 706 // the mask is a vector of integers. 707 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); 708 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 709 710 SDValue AllOnes = DAG.getConstant( 711 APInt::getAllOnesValue(BitTy.getSizeInBits()), MaskTy); 712 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes); 713 714 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); 715 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); 716 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 717 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); 718 } 719 720 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) { 721 EVT VT = Op.getValueType(); 722 723 // Make sure that the SRA and SHL instructions are available. 724 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || 725 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand) 726 return DAG.UnrollVectorOp(Op.getNode()); 727 728 SDLoc DL(Op); 729 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT(); 730 731 unsigned BW = VT.getScalarType().getSizeInBits(); 732 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits(); 733 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT); 734 735 Op = Op.getOperand(0); 736 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz); 737 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); 738 } 739 740 // Generically expand a vector anyext in register to a shuffle of the relevant 741 // lanes into the appropriate locations, with other lanes left undef. 742 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) { 743 SDLoc DL(Op); 744 EVT VT = Op.getValueType(); 745 int NumElements = VT.getVectorNumElements(); 746 SDValue Src = Op.getOperand(0); 747 EVT SrcVT = Src.getValueType(); 748 int NumSrcElements = SrcVT.getVectorNumElements(); 749 750 // Build a base mask of undef shuffles. 751 SmallVector<int, 16> ShuffleMask; 752 ShuffleMask.resize(NumSrcElements, -1); 753 754 // Place the extended lanes into the correct locations. 755 int ExtLaneScale = NumSrcElements / NumElements; 756 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0; 757 for (int i = 0; i < NumElements; ++i) 758 ShuffleMask[i * ExtLaneScale + EndianOffset] = i; 759 760 return DAG.getNode( 761 ISD::BITCAST, DL, VT, 762 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask)); 763 } 764 765 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) { 766 SDLoc DL(Op); 767 EVT VT = Op.getValueType(); 768 SDValue Src = Op.getOperand(0); 769 EVT SrcVT = Src.getValueType(); 770 771 // First build an any-extend node which can be legalized above when we 772 // recurse through it. 773 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT); 774 775 // Now we need sign extend. Do this by shifting the elements. Even if these 776 // aren't legal operations, they have a better chance of being legalized 777 // without full scalarization than the sign extension does. 778 unsigned EltWidth = VT.getVectorElementType().getSizeInBits(); 779 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits(); 780 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT); 781 return DAG.getNode(ISD::SRA, DL, VT, 782 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), 783 ShiftAmount); 784 } 785 786 // Generically expand a vector zext in register to a shuffle of the relevant 787 // lanes into the appropriate locations, a blend of zero into the high bits, 788 // and a bitcast to the wider element type. 789 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) { 790 SDLoc DL(Op); 791 EVT VT = Op.getValueType(); 792 int NumElements = VT.getVectorNumElements(); 793 SDValue Src = Op.getOperand(0); 794 EVT SrcVT = Src.getValueType(); 795 int NumSrcElements = SrcVT.getVectorNumElements(); 796 797 // Build up a zero vector to blend into this one. 798 EVT SrcScalarVT = SrcVT.getScalarType(); 799 SDValue ScalarZero = DAG.getTargetConstant(0, SrcScalarVT); 800 SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero); 801 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands); 802 803 // Shuffle the incoming lanes into the correct position, and pull all other 804 // lanes from the zero vector. 805 SmallVector<int, 16> ShuffleMask; 806 ShuffleMask.reserve(NumSrcElements); 807 for (int i = 0; i < NumSrcElements; ++i) 808 ShuffleMask.push_back(i); 809 810 int ExtLaneScale = NumSrcElements / NumElements; 811 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0; 812 for (int i = 0; i < NumElements; ++i) 813 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i; 814 815 return DAG.getNode(ISD::BITCAST, DL, VT, 816 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask)); 817 } 818 819 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) { 820 EVT VT = Op.getValueType(); 821 822 // Generate a byte wise shuffle mask for the BSWAP. 823 SmallVector<int, 16> ShuffleMask; 824 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8; 825 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I) 826 for (int J = ScalarSizeInBytes - 1; J >= 0; --J) 827 ShuffleMask.push_back((I * ScalarSizeInBytes) + J); 828 829 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size()); 830 831 // Only emit a shuffle if the mask is legal. 832 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT)) 833 return DAG.UnrollVectorOp(Op.getNode()); 834 835 SDLoc DL(Op); 836 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0)); 837 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT), 838 ShuffleMask.data()); 839 return DAG.getNode(ISD::BITCAST, DL, VT, Op); 840 } 841 842 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) { 843 // Implement VSELECT in terms of XOR, AND, OR 844 // on platforms which do not support blend natively. 845 SDLoc DL(Op); 846 847 SDValue Mask = Op.getOperand(0); 848 SDValue Op1 = Op.getOperand(1); 849 SDValue Op2 = Op.getOperand(2); 850 851 EVT VT = Mask.getValueType(); 852 853 // If we can't even use the basic vector operations of 854 // AND,OR,XOR, we will have to scalarize the op. 855 // Notice that the operation may be 'promoted' which means that it is 856 // 'bitcasted' to another type which is handled. 857 // This operation also isn't safe with AND, OR, XOR when the boolean 858 // type is 0/1 as we need an all ones vector constant to mask with. 859 // FIXME: Sign extend 1 to all ones if thats legal on the target. 860 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand || 861 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand || 862 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand || 863 TLI.getBooleanContents(Op1.getValueType()) != 864 TargetLowering::ZeroOrNegativeOneBooleanContent) 865 return DAG.UnrollVectorOp(Op.getNode()); 866 867 // If the mask and the type are different sizes, unroll the vector op. This 868 // can occur when getSetCCResultType returns something that is different in 869 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8. 870 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits()) 871 return DAG.UnrollVectorOp(Op.getNode()); 872 873 // Bitcast the operands to be the same type as the mask. 874 // This is needed when we select between FP types because 875 // the mask is a vector of integers. 876 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); 877 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); 878 879 SDValue AllOnes = DAG.getConstant( 880 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT); 881 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); 882 883 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); 884 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); 885 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); 886 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); 887 } 888 889 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) { 890 EVT VT = Op.getOperand(0).getValueType(); 891 SDLoc DL(Op); 892 893 // Make sure that the SINT_TO_FP and SRL instructions are available. 894 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || 895 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) 896 return DAG.UnrollVectorOp(Op.getNode()); 897 898 EVT SVT = VT.getScalarType(); 899 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) && 900 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide"); 901 902 unsigned BW = SVT.getSizeInBits(); 903 SDValue HalfWord = DAG.getConstant(BW/2, VT); 904 905 // Constants to clear the upper part of the word. 906 // Notice that we can also use SHL+SHR, but using a constant is slightly 907 // faster on x86. 908 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF; 909 SDValue HalfWordMask = DAG.getConstant(HWMask, VT); 910 911 // Two to the power of half-word-size. 912 SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType()); 913 914 // Clear upper part of LO, lower HI 915 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord); 916 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask); 917 918 // Convert hi and lo to floats 919 // Convert the hi part back to the upper values 920 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); 921 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW); 922 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO); 923 924 // Add the two halves 925 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO); 926 } 927 928 929 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) { 930 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { 931 SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType()); 932 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), 933 Zero, Op.getOperand(0)); 934 } 935 return DAG.UnrollVectorOp(Op.getNode()); 936 } 937 938 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) { 939 EVT VT = Op.getValueType(); 940 unsigned NumElems = VT.getVectorNumElements(); 941 EVT EltVT = VT.getVectorElementType(); 942 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2); 943 EVT TmpEltVT = LHS.getValueType().getVectorElementType(); 944 SDLoc dl(Op); 945 SmallVector<SDValue, 8> Ops(NumElems); 946 for (unsigned i = 0; i < NumElems; ++i) { 947 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, 948 DAG.getConstant(i, TLI.getVectorIdxTy())); 949 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, 950 DAG.getConstant(i, TLI.getVectorIdxTy())); 951 Ops[i] = DAG.getNode(ISD::SETCC, dl, 952 TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT), 953 LHSElem, RHSElem, CC); 954 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i], 955 DAG.getConstant(APInt::getAllOnesValue 956 (EltVT.getSizeInBits()), EltVT), 957 DAG.getConstant(0, EltVT)); 958 } 959 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); 960 } 961 962 } 963 964 bool SelectionDAG::LegalizeVectors() { 965 return VectorLegalizer(*this).Run(); 966 } 967