| /external/qemu/target-mips/ |
| helper.c | 290 } lui, lw, srl; member in struct:__anon34776
294 {0x00, 0x3c1b0000, 0xffff0000}, /* 0x3c1b803f : lui k1,%hi(pgd_current_p) */
300 {0x00, 0x3c1b0000, 0xffff0000}, /* 0x3c1b803f : lui k1,%hi(pgd_current_p) */
310 lui_ins = ldl_phys(ebase + handlers[i].lui.off);
313 if (((lui_ins & handlers[i].lui.mask) == handlers[i].lui.op) &&
|
| /external/chromium_org/v8/src/mips/ |
| assembler-mips.cc | 205 // specially coded on MIPS means that it is a lui/ori instruction, and that is
575 return opcode == LUI;
1766 void Assembler::lui(Register rd, int32_t j) { function in class:v8::Assembler
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| /external/chromium_org/v8/src/mips64/ |
| assembler-mips64.cc | 183 // specially coded on MIPS means that it is a lui/ori instruction, and that is
547 return opcode == LUI;
1903 void Assembler::lui(Register rd, int32_t j) { function in class:v8::Assembler
[all...] |
