1 //===-- Mips16ISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips16 ----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Subclass of MipsDAGToDAGISel specialized for mips16. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips16ISelDAGToDAG.h" 15 #include "MCTargetDesc/MipsBaseInfo.h" 16 #include "Mips.h" 17 #include "MipsAnalyzeImmediate.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsRegisterInfo.h" 20 #include "llvm/CodeGen/MachineConstantPool.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/SelectionDAGNodes.h" 26 #include "llvm/IR/CFG.h" 27 #include "llvm/IR/GlobalValue.h" 28 #include "llvm/IR/Instructions.h" 29 #include "llvm/IR/Intrinsics.h" 30 #include "llvm/IR/Type.h" 31 #include "llvm/Support/Debug.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/raw_ostream.h" 34 #include "llvm/Target/TargetMachine.h" 35 using namespace llvm; 36 37 #define DEBUG_TYPE "mips-isel" 38 39 bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { 40 if (!Subtarget->inMips16Mode()) 41 return false; 42 return MipsDAGToDAGISel::runOnMachineFunction(MF); 43 } 44 /// Select multiply instructions. 45 std::pair<SDNode*, SDNode*> 46 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty, 47 bool HasLo, bool HasHi) { 48 SDNode *Lo = nullptr, *Hi = nullptr; 49 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0), 50 N->getOperand(1)); 51 SDValue InFlag = SDValue(Mul, 0); 52 53 if (HasLo) { 54 unsigned Opcode = Mips::Mflo16; 55 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag); 56 InFlag = SDValue(Lo, 1); 57 } 58 if (HasHi) { 59 unsigned Opcode = Mips::Mfhi16; 60 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag); 61 } 62 return std::make_pair(Lo, Hi); 63 } 64 65 void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { 66 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 67 68 if (!MipsFI->globalBaseRegSet()) 69 return; 70 71 MachineBasicBlock &MBB = MF.front(); 72 MachineBasicBlock::iterator I = MBB.begin(); 73 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 74 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 75 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 76 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); 77 const TargetRegisterClass *RC = 78 (const TargetRegisterClass*)&Mips::CPU16RegsRegClass; 79 80 V0 = RegInfo.createVirtualRegister(RC); 81 V1 = RegInfo.createVirtualRegister(RC); 82 V2 = RegInfo.createVirtualRegister(RC); 83 84 BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0). 85 addReg(V1, RegState::Define). 86 addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI). 87 addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); 88 89 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); 90 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg) 91 .addReg(V1).addReg(V2); 92 } 93 94 // Insert instructions to initialize the Mips16 SP Alias register in the 95 // first MBB of the function. 96 // 97 void Mips16DAGToDAGISel::initMips16SPAliasReg(MachineFunction &MF) { 98 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 99 100 if (!MipsFI->mips16SPAliasRegSet()) 101 return; 102 103 MachineBasicBlock &MBB = MF.front(); 104 MachineBasicBlock::iterator I = MBB.begin(); 105 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 106 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 107 unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg(); 108 109 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg) 110 .addReg(Mips::SP); 111 } 112 113 void Mips16DAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) { 114 initGlobalBaseReg(MF); 115 initMips16SPAliasReg(MF); 116 } 117 118 /// getMips16SPAliasReg - Output the instructions required to put the 119 /// SP into a Mips16 accessible aliased register. 120 SDValue Mips16DAGToDAGISel::getMips16SPAliasReg() { 121 unsigned Mips16SPAliasReg = 122 MF->getInfo<MipsFunctionInfo>()->getMips16SPAliasReg(); 123 return CurDAG->getRegister(Mips16SPAliasReg, 124 getTargetLowering()->getPointerTy()); 125 } 126 127 void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) { 128 SDValue AliasFPReg = CurDAG->getRegister(Mips::S0, 129 getTargetLowering()->getPointerTy()); 130 if (Parent) { 131 switch (Parent->getOpcode()) { 132 case ISD::LOAD: { 133 LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent); 134 switch (SD->getMemoryVT().getSizeInBits()) { 135 case 8: 136 case 16: 137 AliasReg = TM.getFrameLowering()->hasFP(*MF)? 138 AliasFPReg: getMips16SPAliasReg(); 139 return; 140 } 141 break; 142 } 143 case ISD::STORE: { 144 StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent); 145 switch (SD->getMemoryVT().getSizeInBits()) { 146 case 8: 147 case 16: 148 AliasReg = TM.getFrameLowering()->hasFP(*MF)? 149 AliasFPReg: getMips16SPAliasReg(); 150 return; 151 } 152 break; 153 } 154 } 155 } 156 AliasReg = CurDAG->getRegister(Mips::SP, getTargetLowering()->getPointerTy()); 157 return; 158 159 } 160 161 bool Mips16DAGToDAGISel::selectAddr16( 162 SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset, 163 SDValue &Alias) { 164 EVT ValTy = Addr.getValueType(); 165 166 Alias = CurDAG->getTargetConstant(0, ValTy); 167 168 // if Address is FI, get the TargetFrameIndex. 169 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 170 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 171 Offset = CurDAG->getTargetConstant(0, ValTy); 172 getMips16SPRefReg(Parent, Alias); 173 return true; 174 } 175 // on PIC code Load GA 176 if (Addr.getOpcode() == MipsISD::Wrapper) { 177 Base = Addr.getOperand(0); 178 Offset = Addr.getOperand(1); 179 return true; 180 } 181 if (TM.getRelocationModel() != Reloc::PIC_) { 182 if ((Addr.getOpcode() == ISD::TargetExternalSymbol || 183 Addr.getOpcode() == ISD::TargetGlobalAddress)) 184 return false; 185 } 186 // Addresses of the form FI+const or FI|const 187 if (CurDAG->isBaseWithConstantOffset(Addr)) { 188 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)); 189 if (isInt<16>(CN->getSExtValue())) { 190 191 // If the first operand is a FI, get the TargetFI Node 192 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode> 193 (Addr.getOperand(0))) { 194 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 195 getMips16SPRefReg(Parent, Alias); 196 } 197 else 198 Base = Addr.getOperand(0); 199 200 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy); 201 return true; 202 } 203 } 204 // Operand is a result from an ADD. 205 if (Addr.getOpcode() == ISD::ADD) { 206 // When loading from constant pools, load the lower address part in 207 // the instruction itself. Example, instead of: 208 // lui $2, %hi($CPI1_0) 209 // addiu $2, $2, %lo($CPI1_0) 210 // lwc1 $f0, 0($2) 211 // Generate: 212 // lui $2, %hi($CPI1_0) 213 // lwc1 $f0, %lo($CPI1_0)($2) 214 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo || 215 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) { 216 SDValue Opnd0 = Addr.getOperand(1).getOperand(0); 217 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) || 218 isa<JumpTableSDNode>(Opnd0)) { 219 Base = Addr.getOperand(0); 220 Offset = Opnd0; 221 return true; 222 } 223 } 224 225 // If an indexed floating point load/store can be emitted, return false. 226 const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent); 227 228 if (LS) { 229 if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2()) 230 return false; 231 if (LS->getMemoryVT() == MVT::f64 && Subtarget->hasMips4_32r2()) 232 return false; 233 } 234 } 235 Base = Addr; 236 Offset = CurDAG->getTargetConstant(0, ValTy); 237 return true; 238 } 239 240 /// Select instructions not customized! Used for 241 /// expanded, promoted and normal instructions 242 std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) { 243 unsigned Opcode = Node->getOpcode(); 244 SDLoc DL(Node); 245 246 /// 247 // Instruction Selection not handled by the auto-generated 248 // tablegen selection should be handled here. 249 /// 250 EVT NodeTy = Node->getValueType(0); 251 unsigned MultOpc; 252 253 switch(Opcode) { 254 default: break; 255 256 case ISD::SUBE: 257 case ISD::ADDE: { 258 SDValue InFlag = Node->getOperand(2), CmpLHS; 259 unsigned Opc = InFlag.getOpcode(); (void)Opc; 260 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || 261 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && 262 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); 263 264 unsigned MOp; 265 if (Opcode == ISD::ADDE) { 266 CmpLHS = InFlag.getValue(0); 267 MOp = Mips::AdduRxRyRz16; 268 } else { 269 CmpLHS = InFlag.getOperand(0); 270 MOp = Mips::SubuRxRyRz16; 271 } 272 273 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; 274 275 SDValue LHS = Node->getOperand(0); 276 SDValue RHS = Node->getOperand(1); 277 278 EVT VT = LHS.getValueType(); 279 280 unsigned Sltu_op = Mips::SltuRxRyRz16; 281 SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops); 282 unsigned Addu_op = Mips::AdduRxRyRz16; 283 SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT, 284 SDValue(Carry,0), RHS); 285 286 SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, 287 SDValue(AddCarry,0)); 288 return std::make_pair(true, Result); 289 } 290 291 /// Mul with two results 292 case ISD::SMUL_LOHI: 293 case ISD::UMUL_LOHI: { 294 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16); 295 std::pair<SDNode*, SDNode*> LoHi = selectMULT(Node, MultOpc, DL, NodeTy, 296 true, true); 297 if (!SDValue(Node, 0).use_empty()) 298 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0)); 299 300 if (!SDValue(Node, 1).use_empty()) 301 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0)); 302 303 return std::make_pair(true, nullptr); 304 } 305 306 case ISD::MULHS: 307 case ISD::MULHU: { 308 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16); 309 SDNode *Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second; 310 return std::make_pair(true, Result); 311 } 312 } 313 314 return std::make_pair(false, nullptr); 315 } 316 317 FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) { 318 return new Mips16DAGToDAGISel(TM); 319 } 320