HomeSort by relevance Sort by last modified time
    Searched refs:ArmMir2Lir (Results 1 - 7 of 7) sorted by null

  /art/compiler/dex/quick/arm/
target_arm.cc 69 RegLocation ArmMir2Lir::LocCReturn() {
73 RegLocation ArmMir2Lir::LocCReturnRef() {
77 RegLocation ArmMir2Lir::LocCReturnWide() {
81 RegLocation ArmMir2Lir::LocCReturnFloat() {
85 RegLocation ArmMir2Lir::LocCReturnDouble() {
90 RegStorage ArmMir2Lir::TargetReg(SpecialTargetRegister reg) {
121 RegStorage ArmMir2Lir::GetArgMappingToPhysicalReg(int arg_num) {
138 ResourceMask ArmMir2Lir::GetRegMaskCommon(const RegStorage& reg) const {
142 constexpr ResourceMask ArmMir2Lir::GetRegMaskArm(RegStorage reg) {
149 constexpr ResourceMask ArmMir2Lir::EncodeArmRegList(int reg_list)
    [all...]
utility_arm.cc 72 LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) {
120 int ArmMir2Lir::ModifiedImmediate(uint32_t value) {
149 bool ArmMir2Lir::InexpensiveConstantInt(int32_t value) {
153 bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value) {
157 bool ArmMir2Lir::InexpensiveConstantLong(int64_t value) {
161 bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value) {
173 LIR* ArmMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
207 LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target) {
213 LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
223 LIR* ArmMir2Lir::OpReg(OpKind op, RegStorage r_dest_src)
    [all...]
int_arm.cc 28 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) {
43 LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) {
71 void ArmMir2Lir::UpdateIT(LIR* it, const char* new_guide) {
99 void ArmMir2Lir::OpEndIT(LIR* it) {
122 void ArmMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
155 void ArmMir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1,
206 void ArmMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
230 void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
305 void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {
367 LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target)
    [all...]
call_arm.cc 46 void ArmMir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
94 void ArmMir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) {
150 void ArmMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) {
179 void ArmMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) {
250 void ArmMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) {
313 void ArmMir2Lir::GenMoveException(RegLocation rl_dest) {
327 void ArmMir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) {
340 void ArmMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) {
471 void ArmMir2Lir::GenExitSequence() {
498 void ArmMir2Lir::GenSpecialExitSequence()
    [all...]
fp_arm.cc 23 void ArmMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
69 void ArmMir2Lir::GenArithOpDouble(Instruction::Code opcode,
116 void ArmMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) {
214 void ArmMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias,
265 void ArmMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest,
323 void ArmMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) {
331 void ArmMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) {
357 bool ArmMir2Lir::GenInlinedAbsFloat(CallInfo* info) {
375 bool ArmMir2Lir::GenInlinedAbsDouble(CallInfo* info) {
402 bool ArmMir2Lir::GenInlinedSqrt(CallInfo* info)
    [all...]
codegen_arm.h 25 class ArmMir2Lir FINAL : public Mir2Lir {
27 ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
assemble_arm.cc 79 const ArmEncodingMap ArmMir2Lir::EncodingMap[kArmLast] = {
    [all...]

Completed in 102 milliseconds