1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the X86MCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/X86MCTargetDesc.h" 15 #include "MCTargetDesc/X86BaseInfo.h" 16 #include "MCTargetDesc/X86FixupKinds.h" 17 #include "llvm/MC/MCCodeEmitter.h" 18 #include "llvm/MC/MCContext.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/MC/MCSymbol.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "mccodeemitter" 30 31 namespace { 32 class X86MCCodeEmitter : public MCCodeEmitter { 33 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION; 34 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION; 35 const MCInstrInfo &MCII; 36 MCContext &Ctx; 37 public: 38 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 39 : MCII(mcii), Ctx(ctx) { 40 } 41 42 ~X86MCCodeEmitter() {} 43 44 bool is64BitMode(const MCSubtargetInfo &STI) const { 45 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 46 } 47 48 bool is32BitMode(const MCSubtargetInfo &STI) const { 49 return (STI.getFeatureBits() & X86::Mode32Bit) != 0; 50 } 51 52 bool is16BitMode(const MCSubtargetInfo &STI) const { 53 return (STI.getFeatureBits() & X86::Mode16Bit) != 0; 54 } 55 56 /// Is16BitMemOperand - Return true if the specified instruction has 57 /// a 16-bit memory operand. Op specifies the operand # of the memoperand. 58 bool Is16BitMemOperand(const MCInst &MI, unsigned Op, 59 const MCSubtargetInfo &STI) const { 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 63 64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && 65 Disp.isImm() && Disp.getImm() < 0x10000) 66 return true; 67 if ((BaseReg.getReg() != 0 && 68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 69 (IndexReg.getReg() != 0 && 70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 71 return true; 72 return false; 73 } 74 75 unsigned GetX86RegNum(const MCOperand &MO) const { 76 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; 77 } 78 79 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range 80 // 0-7 and the difference between the 2 groups is given by the REX prefix. 81 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded 82 // in 1's complement form, example: 83 // 84 // ModRM field => XMM9 => 1 85 // VEX.VVVV => XMM9 => ~9 86 // 87 // See table 4-35 of Intel AVX Programming Reference for details. 88 unsigned char getVEXRegisterEncoding(const MCInst &MI, 89 unsigned OpNum) const { 90 unsigned SrcReg = MI.getOperand(OpNum).getReg(); 91 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum)); 92 if (X86II::isX86_64ExtendedReg(SrcReg)) 93 SrcRegNum |= 8; 94 95 // The registers represented through VEX_VVVV should 96 // be encoded in 1's complement form. 97 return (~SrcRegNum) & 0xf; 98 } 99 100 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI, 101 unsigned OpNum) const { 102 assert(X86::K0 != MI.getOperand(OpNum).getReg() && 103 "Invalid mask register as write-mask!"); 104 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum)); 105 return MaskRegNum; 106 } 107 108 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { 109 OS << (char)C; 110 ++CurByte; 111 } 112 113 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, 114 raw_ostream &OS) const { 115 // Output the constant in little endian byte order. 116 for (unsigned i = 0; i != Size; ++i) { 117 EmitByte(Val & 255, CurByte, OS); 118 Val >>= 8; 119 } 120 } 121 122 void EmitImmediate(const MCOperand &Disp, SMLoc Loc, 123 unsigned ImmSize, MCFixupKind FixupKind, 124 unsigned &CurByte, raw_ostream &OS, 125 SmallVectorImpl<MCFixup> &Fixups, 126 int ImmOffset = 0) const; 127 128 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 129 unsigned RM) { 130 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 131 return RM | (RegOpcode << 3) | (Mod << 6); 132 } 133 134 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, 135 unsigned &CurByte, raw_ostream &OS) const { 136 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS); 137 } 138 139 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base, 140 unsigned &CurByte, raw_ostream &OS) const { 141 // SIB byte is in the same format as the ModRMByte. 142 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS); 143 } 144 145 146 void EmitMemModRMByte(const MCInst &MI, unsigned Op, 147 unsigned RegOpcodeField, 148 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, 149 SmallVectorImpl<MCFixup> &Fixups, 150 const MCSubtargetInfo &STI) const; 151 152 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 153 SmallVectorImpl<MCFixup> &Fixups, 154 const MCSubtargetInfo &STI) const override; 155 156 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 157 const MCInst &MI, const MCInstrDesc &Desc, 158 raw_ostream &OS) const; 159 160 void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand, 161 const MCInst &MI, raw_ostream &OS) const; 162 163 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 164 const MCInst &MI, const MCInstrDesc &Desc, 165 const MCSubtargetInfo &STI, 166 raw_ostream &OS) const; 167 }; 168 169 } // end anonymous namespace 170 171 172 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, 173 const MCRegisterInfo &MRI, 174 const MCSubtargetInfo &STI, 175 MCContext &Ctx) { 176 return new X86MCCodeEmitter(MCII, Ctx); 177 } 178 179 /// isDisp8 - Return true if this signed displacement fits in a 8-bit 180 /// sign-extended field. 181 static bool isDisp8(int Value) { 182 return Value == (signed char)Value; 183 } 184 185 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit 186 /// compressed dispacement field. 187 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) { 188 assert((TSFlags & X86II::EncodingMask) >> X86II::EncodingShift == X86II::EVEX && 189 "Compressed 8-bit displacement is only valid for EVEX inst."); 190 191 unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask; 192 unsigned CD8V = (TSFlags >> X86II::EVEX_CD8VShift) & X86II::EVEX_CD8VMask; 193 194 if (CD8V == 0 && CD8E == 0) { 195 CValue = Value; 196 return isDisp8(Value); 197 } 198 199 unsigned MemObjSize = 1U << CD8E; 200 if (CD8V & 4) { 201 // Fixed vector length 202 MemObjSize *= 1U << (CD8V & 0x3); 203 } else { 204 // Modified vector length 205 bool EVEX_b = (TSFlags >> X86II::VEXShift) & X86II::EVEX_B; 206 if (!EVEX_b) { 207 unsigned EVEX_LL = ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) ? 1 : 0; 208 EVEX_LL += ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2) ? 2 : 0; 209 assert(EVEX_LL < 3 && ""); 210 211 unsigned NumElems = (1U << (EVEX_LL + 4)) / MemObjSize; 212 NumElems /= 1U << (CD8V & 0x3); 213 214 MemObjSize *= NumElems; 215 } 216 } 217 218 unsigned MemObjMask = MemObjSize - 1; 219 assert((MemObjSize & MemObjMask) == 0 && "Invalid memory object size."); 220 221 if (Value & MemObjMask) // Unaligned offset 222 return false; 223 Value /= (int)MemObjSize; 224 bool Ret = (Value == (signed char)Value); 225 226 if (Ret) 227 CValue = Value; 228 return Ret; 229 } 230 231 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate 232 /// in an instruction with the specified TSFlags. 233 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { 234 unsigned Size = X86II::getSizeOfImm(TSFlags); 235 bool isPCRel = X86II::isImmPCRel(TSFlags); 236 237 if (X86II::isImmSigned(TSFlags)) { 238 switch (Size) { 239 default: llvm_unreachable("Unsupported signed fixup size!"); 240 case 4: return MCFixupKind(X86::reloc_signed_4byte); 241 } 242 } 243 return MCFixup::getKindForSize(Size, isPCRel); 244 } 245 246 /// Is32BitMemOperand - Return true if the specified instruction has 247 /// a 32-bit memory operand. Op specifies the operand # of the memoperand. 248 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) { 249 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 250 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 251 252 if ((BaseReg.getReg() != 0 && 253 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 254 (IndexReg.getReg() != 0 && 255 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 256 return true; 257 return false; 258 } 259 260 /// Is64BitMemOperand - Return true if the specified instruction has 261 /// a 64-bit memory operand. Op specifies the operand # of the memoperand. 262 #ifndef NDEBUG 263 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) { 264 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 265 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 266 267 if ((BaseReg.getReg() != 0 && 268 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 269 (IndexReg.getReg() != 0 && 270 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 271 return true; 272 return false; 273 } 274 #endif 275 276 /// StartsWithGlobalOffsetTable - Check if this expression starts with 277 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form 278 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF 279 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that 280 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start 281 /// of a binary expression. 282 enum GlobalOffsetTableExprKind { 283 GOT_None, 284 GOT_Normal, 285 GOT_SymDiff 286 }; 287 static GlobalOffsetTableExprKind 288 StartsWithGlobalOffsetTable(const MCExpr *Expr) { 289 const MCExpr *RHS = nullptr; 290 if (Expr->getKind() == MCExpr::Binary) { 291 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr); 292 Expr = BE->getLHS(); 293 RHS = BE->getRHS(); 294 } 295 296 if (Expr->getKind() != MCExpr::SymbolRef) 297 return GOT_None; 298 299 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 300 const MCSymbol &S = Ref->getSymbol(); 301 if (S.getName() != "_GLOBAL_OFFSET_TABLE_") 302 return GOT_None; 303 if (RHS && RHS->getKind() == MCExpr::SymbolRef) 304 return GOT_SymDiff; 305 return GOT_Normal; 306 } 307 308 static bool HasSecRelSymbolRef(const MCExpr *Expr) { 309 if (Expr->getKind() == MCExpr::SymbolRef) { 310 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 311 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL; 312 } 313 return false; 314 } 315 316 void X86MCCodeEmitter:: 317 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size, 318 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, 319 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const { 320 const MCExpr *Expr = nullptr; 321 if (DispOp.isImm()) { 322 // If this is a simple integer displacement that doesn't require a 323 // relocation, emit it now. 324 if (FixupKind != FK_PCRel_1 && 325 FixupKind != FK_PCRel_2 && 326 FixupKind != FK_PCRel_4) { 327 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS); 328 return; 329 } 330 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx); 331 } else { 332 Expr = DispOp.getExpr(); 333 } 334 335 // If we have an immoffset, add it to the expression. 336 if ((FixupKind == FK_Data_4 || 337 FixupKind == FK_Data_8 || 338 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) { 339 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr); 340 if (Kind != GOT_None) { 341 assert(ImmOffset == 0); 342 343 if (Size == 8) { 344 FixupKind = MCFixupKind(X86::reloc_global_offset_table8); 345 } else { 346 assert(Size == 4); 347 FixupKind = MCFixupKind(X86::reloc_global_offset_table); 348 } 349 350 if (Kind == GOT_Normal) 351 ImmOffset = CurByte; 352 } else if (Expr->getKind() == MCExpr::SymbolRef) { 353 if (HasSecRelSymbolRef(Expr)) { 354 FixupKind = MCFixupKind(FK_SecRel_4); 355 } 356 } else if (Expr->getKind() == MCExpr::Binary) { 357 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr); 358 if (HasSecRelSymbolRef(Bin->getLHS()) 359 || HasSecRelSymbolRef(Bin->getRHS())) { 360 FixupKind = MCFixupKind(FK_SecRel_4); 361 } 362 } 363 } 364 365 // If the fixup is pc-relative, we need to bias the value to be relative to 366 // the start of the field, not the end of the field. 367 if (FixupKind == FK_PCRel_4 || 368 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || 369 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load)) 370 ImmOffset -= 4; 371 if (FixupKind == FK_PCRel_2) 372 ImmOffset -= 2; 373 if (FixupKind == FK_PCRel_1) 374 ImmOffset -= 1; 375 376 if (ImmOffset) 377 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx), 378 Ctx); 379 380 // Emit a symbolic constant as a fixup and 4 zeros. 381 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc)); 382 EmitConstant(0, Size, CurByte, OS); 383 } 384 385 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, 386 unsigned RegOpcodeField, 387 uint64_t TSFlags, unsigned &CurByte, 388 raw_ostream &OS, 389 SmallVectorImpl<MCFixup> &Fixups, 390 const MCSubtargetInfo &STI) const{ 391 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 392 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg); 393 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); 394 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 395 unsigned BaseReg = Base.getReg(); 396 unsigned char Encoding = (TSFlags & X86II::EncodingMask) >> 397 X86II::EncodingShift; 398 bool HasEVEX = (Encoding == X86II::EVEX); 399 400 // Handle %rip relative addressing. 401 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 402 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode"); 403 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); 404 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 405 406 unsigned FixupKind = X86::reloc_riprel_4byte; 407 408 // movq loads are handled with a special relocation form which allows the 409 // linker to eliminate some loads for GOT references which end up in the 410 // same linkage unit. 411 if (MI.getOpcode() == X86::MOV64rm) 412 FixupKind = X86::reloc_riprel_4byte_movq_load; 413 414 // rip-relative addressing is actually relative to the *next* instruction. 415 // Since an immediate can follow the mod/rm byte for an instruction, this 416 // means that we need to bias the immediate field of the instruction with 417 // the size of the immediate field. If we have this case, add it into the 418 // expression to emit. 419 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; 420 421 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), 422 CurByte, OS, Fixups, -ImmSize); 423 return; 424 } 425 426 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; 427 428 // 16-bit addressing forms of the ModR/M byte have a different encoding for 429 // the R/M field and are far more limited in which registers can be used. 430 if (Is16BitMemOperand(MI, Op, STI)) { 431 if (BaseReg) { 432 // For 32-bit addressing, the row and column values in Table 2-2 are 433 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with 434 // some special cases. And GetX86RegNum reflects that numbering. 435 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A, 436 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only 437 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order, 438 // while values 0-3 indicate the allowed combinations (base+index) of 439 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI. 440 // 441 // R16Table[] is a lookup from the normal RegNo, to the row values from 442 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed. 443 static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 }; 444 unsigned RMfield = R16Table[BaseRegNo]; 445 446 assert(RMfield && "invalid 16-bit base register"); 447 448 if (IndexReg.getReg()) { 449 unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)]; 450 451 assert(IndexReg16 && "invalid 16-bit index register"); 452 // We must have one of SI/DI (4,5), and one of BP/BX (6,7). 453 assert(((IndexReg16 ^ RMfield) & 2) && 454 "invalid 16-bit base/index register combination"); 455 assert(Scale.getImm() == 1 && 456 "invalid scale for 16-bit memory reference"); 457 458 // Allow base/index to appear in either order (although GAS doesn't). 459 if (IndexReg16 & 2) 460 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1); 461 else 462 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1); 463 } 464 465 if (Disp.isImm() && isDisp8(Disp.getImm())) { 466 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 467 // There is no displacement; just the register. 468 EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS); 469 return; 470 } 471 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded. 472 EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS); 473 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 474 return; 475 } 476 // This is the [REG]+disp16 case. 477 EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS); 478 } else { 479 // There is no BaseReg; this is the plain [disp16] case. 480 EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS); 481 } 482 483 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases. 484 EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups); 485 return; 486 } 487 488 // Determine whether a SIB byte is needed. 489 // If no BaseReg, issue a RIP relative instruction only if the MCE can 490 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 491 // 2-7) and absolute references. 492 493 if (// The SIB byte must be used if there is an index register. 494 IndexReg.getReg() == 0 && 495 // The SIB byte must be used if the base is ESP/RSP/R12, all of which 496 // encode to an R/M value of 4, which indicates that a SIB byte is 497 // present. 498 BaseRegNo != N86::ESP && 499 // If there is no base register and we're in 64-bit mode, we need a SIB 500 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 501 (!is64BitMode(STI) || BaseReg != 0)) { 502 503 if (BaseReg == 0) { // [disp32] in X86-32 mode 504 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 505 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups); 506 return; 507 } 508 509 // If the base is not EBP/ESP and there is no displacement, use simple 510 // indirect register encoding, this handles addresses like [EAX]. The 511 // encoding for [EBP] with no displacement means [disp32] so we handle it 512 // by emitting a displacement of 0 below. 513 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 514 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 515 return; 516 } 517 518 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 519 if (Disp.isImm()) { 520 if (!HasEVEX && isDisp8(Disp.getImm())) { 521 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 522 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 523 return; 524 } 525 // Try EVEX compressed 8-bit displacement first; if failed, fall back to 526 // 32-bit displacement. 527 int CDisp8 = 0; 528 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 529 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 530 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, 531 CDisp8 - Disp.getImm()); 532 return; 533 } 534 } 535 536 // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 537 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); 538 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS, 539 Fixups); 540 return; 541 } 542 543 // We need a SIB byte, so start by outputting the ModR/M byte first 544 assert(IndexReg.getReg() != X86::ESP && 545 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 546 547 bool ForceDisp32 = false; 548 bool ForceDisp8 = false; 549 int CDisp8 = 0; 550 int ImmOffset = 0; 551 if (BaseReg == 0) { 552 // If there is no base register, we emit the special case SIB byte with 553 // MOD=0, BASE=5, to JUST get the index, scale, and displacement. 554 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 555 ForceDisp32 = true; 556 } else if (!Disp.isImm()) { 557 // Emit the normal disp32 encoding. 558 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 559 ForceDisp32 = true; 560 } else if (Disp.getImm() == 0 && 561 // Base reg can't be anything that ends up with '5' as the base 562 // reg, it is the magic [*] nomenclature that indicates no base. 563 BaseRegNo != N86::EBP) { 564 // Emit no displacement ModR/M byte 565 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 566 } else if (!HasEVEX && isDisp8(Disp.getImm())) { 567 // Emit the disp8 encoding. 568 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 569 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 570 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 571 // Emit the disp8 encoding. 572 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 573 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 574 ImmOffset = CDisp8 - Disp.getImm(); 575 } else { 576 // Emit the normal disp32 encoding. 577 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 578 } 579 580 // Calculate what the SS field value should be... 581 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 582 unsigned SS = SSTable[Scale.getImm()]; 583 584 if (BaseReg == 0) { 585 // Handle the SIB byte for the case where there is no base, see Intel 586 // Manual 2A, table 2-7. The displacement has already been output. 587 unsigned IndexRegNo; 588 if (IndexReg.getReg()) 589 IndexRegNo = GetX86RegNum(IndexReg); 590 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 591 IndexRegNo = 4; 592 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS); 593 } else { 594 unsigned IndexRegNo; 595 if (IndexReg.getReg()) 596 IndexRegNo = GetX86RegNum(IndexReg); 597 else 598 IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 599 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS); 600 } 601 602 // Do we need to output a displacement? 603 if (ForceDisp8) 604 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset); 605 else if (ForceDisp32 || Disp.getImm() != 0) 606 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 607 CurByte, OS, Fixups); 608 } 609 610 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix 611 /// called VEX. 612 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 613 int MemOperand, const MCInst &MI, 614 const MCInstrDesc &Desc, 615 raw_ostream &OS) const { 616 unsigned char Encoding = (TSFlags & X86II::EncodingMask) >> 617 X86II::EncodingShift; 618 bool HasEVEX_K = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K); 619 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 620 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 621 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 622 bool HasEVEX_RC = (TSFlags >> X86II::VEXShift) & X86II::EVEX_RC; 623 624 // VEX_R: opcode externsion equivalent to REX.R in 625 // 1's complement (inverted) form 626 // 627 // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 628 // 0: Same as REX_R=1 (64 bit mode only) 629 // 630 unsigned char VEX_R = 0x1; 631 unsigned char EVEX_R2 = 0x1; 632 633 // VEX_X: equivalent to REX.X, only used when a 634 // register is used for index in SIB Byte. 635 // 636 // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 637 // 0: Same as REX.X=1 (64-bit mode only) 638 unsigned char VEX_X = 0x1; 639 640 // VEX_B: 641 // 642 // 1: Same as REX_B=0 (ignored in 32-bit mode) 643 // 0: Same as REX_B=1 (64 bit mode only) 644 // 645 unsigned char VEX_B = 0x1; 646 647 // VEX_W: opcode specific (use like REX.W, or used for 648 // opcode extension, or ignored, depending on the opcode byte) 649 unsigned char VEX_W = 0; 650 651 // VEX_5M (VEX m-mmmmm field): 652 // 653 // 0b00000: Reserved for future use 654 // 0b00001: implied 0F leading opcode 655 // 0b00010: implied 0F 38 leading opcode bytes 656 // 0b00011: implied 0F 3A leading opcode bytes 657 // 0b00100-0b11111: Reserved for future use 658 // 0b01000: XOP map select - 08h instructions with imm byte 659 // 0b01001: XOP map select - 09h instructions with no imm byte 660 // 0b01010: XOP map select - 0Ah instructions with imm dword 661 unsigned char VEX_5M = 0; 662 663 // VEX_4V (VEX vvvv field): a register specifier 664 // (in 1's complement form) or 1111 if unused. 665 unsigned char VEX_4V = 0xf; 666 unsigned char EVEX_V2 = 0x1; 667 668 // VEX_L (Vector Length): 669 // 670 // 0: scalar or 128-bit vector 671 // 1: 256-bit vector 672 // 673 unsigned char VEX_L = 0; 674 unsigned char EVEX_L2 = 0; 675 676 // VEX_PP: opcode extension providing equivalent 677 // functionality of a SIMD prefix 678 // 679 // 0b00: None 680 // 0b01: 66 681 // 0b10: F3 682 // 0b11: F2 683 // 684 unsigned char VEX_PP = 0; 685 686 // EVEX_U 687 unsigned char EVEX_U = 1; // Always '1' so far 688 689 // EVEX_z 690 unsigned char EVEX_z = 0; 691 692 // EVEX_b 693 unsigned char EVEX_b = 0; 694 695 // EVEX_rc 696 unsigned char EVEX_rc = 0; 697 698 // EVEX_aaa 699 unsigned char EVEX_aaa = 0; 700 701 bool EncodeRC = false; 702 703 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W) 704 VEX_W = 1; 705 706 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) 707 VEX_L = 1; 708 if (((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2)) 709 EVEX_L2 = 1; 710 711 if (HasEVEX_K && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_Z)) 712 EVEX_z = 1; 713 714 if (((TSFlags >> X86II::VEXShift) & X86II::EVEX_B)) 715 EVEX_b = 1; 716 717 switch (TSFlags & X86II::OpPrefixMask) { 718 default: break; // VEX_PP already correct 719 case X86II::PD: VEX_PP = 0x1; break; // 66 720 case X86II::XS: VEX_PP = 0x2; break; // F3 721 case X86II::XD: VEX_PP = 0x3; break; // F2 722 } 723 724 switch (TSFlags & X86II::OpMapMask) { 725 default: llvm_unreachable("Invalid prefix!"); 726 case X86II::TB: VEX_5M = 0x1; break; // 0F 727 case X86II::T8: VEX_5M = 0x2; break; // 0F 38 728 case X86II::TA: VEX_5M = 0x3; break; // 0F 3A 729 case X86II::XOP8: VEX_5M = 0x8; break; 730 case X86II::XOP9: VEX_5M = 0x9; break; 731 case X86II::XOPA: VEX_5M = 0xA; break; 732 } 733 734 // Classify VEX_B, VEX_4V, VEX_R, VEX_X 735 unsigned NumOps = Desc.getNumOperands(); 736 unsigned CurOp = X86II::getOperandBias(Desc); 737 738 switch (TSFlags & X86II::FormMask) { 739 default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!"); 740 case X86II::RawFrm: 741 break; 742 case X86II::MRMDestMem: { 743 // MRMDestMem instructions forms: 744 // MemAddr, src1(ModR/M) 745 // MemAddr, src1(VEX_4V), src2(ModR/M) 746 // MemAddr, src1(ModR/M), imm8 747 // 748 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand + 749 X86::AddrBaseReg).getReg())) 750 VEX_B = 0x0; 751 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand + 752 X86::AddrIndexReg).getReg())) 753 VEX_X = 0x0; 754 if (X86II::is32ExtendedReg(MI.getOperand(MemOperand + 755 X86::AddrIndexReg).getReg())) 756 EVEX_V2 = 0x0; 757 758 CurOp += X86::AddrNumOperands; 759 760 if (HasEVEX_K) 761 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 762 763 if (HasVEX_4V) { 764 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 765 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 766 EVEX_V2 = 0x0; 767 CurOp++; 768 } 769 770 const MCOperand &MO = MI.getOperand(CurOp); 771 if (MO.isReg()) { 772 if (X86II::isX86_64ExtendedReg(MO.getReg())) 773 VEX_R = 0x0; 774 if (X86II::is32ExtendedReg(MO.getReg())) 775 EVEX_R2 = 0x0; 776 } 777 break; 778 } 779 case X86II::MRMSrcMem: 780 // MRMSrcMem instructions forms: 781 // src1(ModR/M), MemAddr 782 // src1(ModR/M), src2(VEX_4V), MemAddr 783 // src1(ModR/M), MemAddr, imm8 784 // src1(ModR/M), MemAddr, src2(VEX_I8IMM) 785 // 786 // FMA4: 787 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 788 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 789 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 790 VEX_R = 0x0; 791 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 792 EVEX_R2 = 0x0; 793 CurOp++; 794 795 if (HasEVEX_K) 796 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 797 798 if (HasVEX_4V) { 799 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 800 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 801 EVEX_V2 = 0x0; 802 CurOp++; 803 } 804 805 if (X86II::isX86_64ExtendedReg( 806 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 807 VEX_B = 0x0; 808 if (X86II::isX86_64ExtendedReg( 809 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 810 VEX_X = 0x0; 811 if (X86II::is32ExtendedReg(MI.getOperand(MemOperand + 812 X86::AddrIndexReg).getReg())) 813 EVEX_V2 = 0x0; 814 815 if (HasVEX_4VOp3) 816 // Instruction format for 4VOp3: 817 // src1(ModR/M), MemAddr, src3(VEX_4V) 818 // CurOp points to start of the MemoryOperand, 819 // it skips TIED_TO operands if exist, then increments past src1. 820 // CurOp + X86::AddrNumOperands will point to src3. 821 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands); 822 break; 823 case X86II::MRM0m: case X86II::MRM1m: 824 case X86II::MRM2m: case X86II::MRM3m: 825 case X86II::MRM4m: case X86II::MRM5m: 826 case X86II::MRM6m: case X86II::MRM7m: { 827 // MRM[0-9]m instructions forms: 828 // MemAddr 829 // src1(VEX_4V), MemAddr 830 if (HasVEX_4V) { 831 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 832 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 833 EVEX_V2 = 0x0; 834 CurOp++; 835 } 836 837 if (HasEVEX_K) 838 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 839 840 if (X86II::isX86_64ExtendedReg( 841 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 842 VEX_B = 0x0; 843 if (X86II::isX86_64ExtendedReg( 844 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 845 VEX_X = 0x0; 846 break; 847 } 848 case X86II::MRMSrcReg: 849 // MRMSrcReg instructions forms: 850 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 851 // dst(ModR/M), src1(ModR/M) 852 // dst(ModR/M), src1(ModR/M), imm8 853 // 854 // FMA4: 855 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 856 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 857 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 858 VEX_R = 0x0; 859 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 860 EVEX_R2 = 0x0; 861 CurOp++; 862 863 if (HasEVEX_K) 864 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 865 866 if (HasVEX_4V) { 867 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 868 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 869 EVEX_V2 = 0x0; 870 CurOp++; 871 } 872 873 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 874 CurOp++; 875 876 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 877 VEX_B = 0x0; 878 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 879 VEX_X = 0x0; 880 CurOp++; 881 if (HasVEX_4VOp3) 882 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 883 if (EVEX_b) { 884 if (HasEVEX_RC) { 885 unsigned RcOperand = NumOps-1; 886 assert(RcOperand >= CurOp); 887 EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3; 888 } 889 EncodeRC = true; 890 } 891 break; 892 case X86II::MRMDestReg: 893 // MRMDestReg instructions forms: 894 // dst(ModR/M), src(ModR/M) 895 // dst(ModR/M), src(ModR/M), imm8 896 // dst(ModR/M), src1(VEX_4V), src2(ModR/M) 897 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 898 VEX_B = 0x0; 899 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 900 VEX_X = 0x0; 901 CurOp++; 902 903 if (HasEVEX_K) 904 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 905 906 if (HasVEX_4V) { 907 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 908 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 909 EVEX_V2 = 0x0; 910 CurOp++; 911 } 912 913 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 914 VEX_R = 0x0; 915 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 916 EVEX_R2 = 0x0; 917 if (EVEX_b) 918 EncodeRC = true; 919 break; 920 case X86II::MRM0r: case X86II::MRM1r: 921 case X86II::MRM2r: case X86II::MRM3r: 922 case X86II::MRM4r: case X86II::MRM5r: 923 case X86II::MRM6r: case X86II::MRM7r: 924 // MRM0r-MRM7r instructions forms: 925 // dst(VEX_4V), src(ModR/M), imm8 926 if (HasVEX_4V) { 927 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 928 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 929 EVEX_V2 = 0x0; 930 CurOp++; 931 } 932 if (HasEVEX_K) 933 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 934 935 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 936 VEX_B = 0x0; 937 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 938 VEX_X = 0x0; 939 break; 940 } 941 942 if (Encoding == X86II::VEX || Encoding == X86II::XOP) { 943 // VEX opcode prefix can have 2 or 3 bytes 944 // 945 // 3 bytes: 946 // +-----+ +--------------+ +-------------------+ 947 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 948 // +-----+ +--------------+ +-------------------+ 949 // 2 bytes: 950 // +-----+ +-------------------+ 951 // | C5h | | R | vvvv | L | pp | 952 // +-----+ +-------------------+ 953 // 954 // XOP uses a similar prefix: 955 // +-----+ +--------------+ +-------------------+ 956 // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp | 957 // +-----+ +--------------+ +-------------------+ 958 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 959 960 // Can we use the 2 byte VEX prefix? 961 if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { 962 EmitByte(0xC5, CurByte, OS); 963 EmitByte(LastByte | (VEX_R << 7), CurByte, OS); 964 return; 965 } 966 967 // 3 byte VEX prefix 968 EmitByte(Encoding == X86II::XOP ? 0x8F : 0xC4, CurByte, OS); 969 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); 970 EmitByte(LastByte | (VEX_W << 7), CurByte, OS); 971 } else { 972 assert(Encoding == X86II::EVEX && "unknown encoding!"); 973 // EVEX opcode prefix can have 4 bytes 974 // 975 // +-----+ +--------------+ +-------------------+ +------------------------+ 976 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa | 977 // +-----+ +--------------+ +-------------------+ +------------------------+ 978 assert((VEX_5M & 0x3) == VEX_5M 979 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!"); 980 981 VEX_5M &= 0x3; 982 983 EmitByte(0x62, CurByte, OS); 984 EmitByte((VEX_R << 7) | 985 (VEX_X << 6) | 986 (VEX_B << 5) | 987 (EVEX_R2 << 4) | 988 VEX_5M, CurByte, OS); 989 EmitByte((VEX_W << 7) | 990 (VEX_4V << 3) | 991 (EVEX_U << 2) | 992 VEX_PP, CurByte, OS); 993 if (EncodeRC) 994 EmitByte((EVEX_z << 7) | 995 (EVEX_rc << 5) | 996 (EVEX_b << 4) | 997 (EVEX_V2 << 3) | 998 EVEX_aaa, CurByte, OS); 999 else 1000 EmitByte((EVEX_z << 7) | 1001 (EVEX_L2 << 6) | 1002 (VEX_L << 5) | 1003 (EVEX_b << 4) | 1004 (EVEX_V2 << 3) | 1005 EVEX_aaa, CurByte, OS); 1006 } 1007 } 1008 1009 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64 1010 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 1011 /// size, and 3) use of X86-64 extended registers. 1012 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, 1013 const MCInstrDesc &Desc) { 1014 unsigned REX = 0; 1015 if (TSFlags & X86II::REX_W) 1016 REX |= 1 << 3; // set REX.W 1017 1018 if (MI.getNumOperands() == 0) return REX; 1019 1020 unsigned NumOps = MI.getNumOperands(); 1021 // FIXME: MCInst should explicitize the two-addrness. 1022 bool isTwoAddr = NumOps > 1 && 1023 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 1024 1025 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 1026 unsigned i = isTwoAddr ? 1 : 0; 1027 for (; i != NumOps; ++i) { 1028 const MCOperand &MO = MI.getOperand(i); 1029 if (!MO.isReg()) continue; 1030 unsigned Reg = MO.getReg(); 1031 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue; 1032 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything 1033 // that returns non-zero. 1034 REX |= 0x40; // REX fixed encoding prefix 1035 break; 1036 } 1037 1038 switch (TSFlags & X86II::FormMask) { 1039 case X86II::MRMSrcReg: 1040 if (MI.getOperand(0).isReg() && 1041 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 1042 REX |= 1 << 2; // set REX.R 1043 i = isTwoAddr ? 2 : 1; 1044 for (; i != NumOps; ++i) { 1045 const MCOperand &MO = MI.getOperand(i); 1046 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 1047 REX |= 1 << 0; // set REX.B 1048 } 1049 break; 1050 case X86II::MRMSrcMem: { 1051 if (MI.getOperand(0).isReg() && 1052 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 1053 REX |= 1 << 2; // set REX.R 1054 unsigned Bit = 0; 1055 i = isTwoAddr ? 2 : 1; 1056 for (; i != NumOps; ++i) { 1057 const MCOperand &MO = MI.getOperand(i); 1058 if (MO.isReg()) { 1059 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1060 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) 1061 Bit++; 1062 } 1063 } 1064 break; 1065 } 1066 case X86II::MRMXm: 1067 case X86II::MRM0m: case X86II::MRM1m: 1068 case X86II::MRM2m: case X86II::MRM3m: 1069 case X86II::MRM4m: case X86II::MRM5m: 1070 case X86II::MRM6m: case X86II::MRM7m: 1071 case X86II::MRMDestMem: { 1072 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 1073 i = isTwoAddr ? 1 : 0; 1074 if (NumOps > e && MI.getOperand(e).isReg() && 1075 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg())) 1076 REX |= 1 << 2; // set REX.R 1077 unsigned Bit = 0; 1078 for (; i != e; ++i) { 1079 const MCOperand &MO = MI.getOperand(i); 1080 if (MO.isReg()) { 1081 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1082 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) 1083 Bit++; 1084 } 1085 } 1086 break; 1087 } 1088 default: 1089 if (MI.getOperand(0).isReg() && 1090 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 1091 REX |= 1 << 0; // set REX.B 1092 i = isTwoAddr ? 2 : 1; 1093 for (unsigned e = NumOps; i != e; ++i) { 1094 const MCOperand &MO = MI.getOperand(i); 1095 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 1096 REX |= 1 << 2; // set REX.R 1097 } 1098 break; 1099 } 1100 return REX; 1101 } 1102 1103 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed 1104 void X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte, 1105 unsigned SegOperand, 1106 const MCInst &MI, 1107 raw_ostream &OS) const { 1108 // Check for explicit segment override on memory operand. 1109 switch (MI.getOperand(SegOperand).getReg()) { 1110 default: llvm_unreachable("Unknown segment register!"); 1111 case 0: break; 1112 case X86::CS: EmitByte(0x2E, CurByte, OS); break; 1113 case X86::SS: EmitByte(0x36, CurByte, OS); break; 1114 case X86::DS: EmitByte(0x3E, CurByte, OS); break; 1115 case X86::ES: EmitByte(0x26, CurByte, OS); break; 1116 case X86::FS: EmitByte(0x64, CurByte, OS); break; 1117 case X86::GS: EmitByte(0x65, CurByte, OS); break; 1118 } 1119 } 1120 1121 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. 1122 /// 1123 /// MemOperand is the operand # of the start of a memory operand if present. If 1124 /// Not present, it is -1. 1125 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 1126 int MemOperand, const MCInst &MI, 1127 const MCInstrDesc &Desc, 1128 const MCSubtargetInfo &STI, 1129 raw_ostream &OS) const { 1130 1131 // Emit the operand size opcode prefix as needed. 1132 unsigned char OpSize = (TSFlags & X86II::OpSizeMask) >> X86II::OpSizeShift; 1133 if (OpSize == (is16BitMode(STI) ? X86II::OpSize32 : X86II::OpSize16)) 1134 EmitByte(0x66, CurByte, OS); 1135 1136 switch (TSFlags & X86II::OpPrefixMask) { 1137 case X86II::PD: // 66 1138 EmitByte(0x66, CurByte, OS); 1139 break; 1140 case X86II::XS: // F3 1141 EmitByte(0xF3, CurByte, OS); 1142 break; 1143 case X86II::XD: // F2 1144 EmitByte(0xF2, CurByte, OS); 1145 break; 1146 } 1147 1148 // Handle REX prefix. 1149 // FIXME: Can this come before F2 etc to simplify emission? 1150 if (is64BitMode(STI)) { 1151 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc)) 1152 EmitByte(0x40 | REX, CurByte, OS); 1153 } 1154 1155 // 0x0F escape code must be emitted just before the opcode. 1156 switch (TSFlags & X86II::OpMapMask) { 1157 case X86II::TB: // Two-byte opcode map 1158 case X86II::T8: // 0F 38 1159 case X86II::TA: // 0F 3A 1160 EmitByte(0x0F, CurByte, OS); 1161 break; 1162 } 1163 1164 switch (TSFlags & X86II::OpMapMask) { 1165 case X86II::T8: // 0F 38 1166 EmitByte(0x38, CurByte, OS); 1167 break; 1168 case X86II::TA: // 0F 3A 1169 EmitByte(0x3A, CurByte, OS); 1170 break; 1171 } 1172 } 1173 1174 void X86MCCodeEmitter:: 1175 EncodeInstruction(const MCInst &MI, raw_ostream &OS, 1176 SmallVectorImpl<MCFixup> &Fixups, 1177 const MCSubtargetInfo &STI) const { 1178 unsigned Opcode = MI.getOpcode(); 1179 const MCInstrDesc &Desc = MCII.get(Opcode); 1180 uint64_t TSFlags = Desc.TSFlags; 1181 1182 // Pseudo instructions don't get encoded. 1183 if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 1184 return; 1185 1186 unsigned NumOps = Desc.getNumOperands(); 1187 unsigned CurOp = X86II::getOperandBias(Desc); 1188 1189 // Keep track of the current byte being emitted. 1190 unsigned CurByte = 0; 1191 1192 // Encoding type for this instruction. 1193 unsigned char Encoding = (TSFlags & X86II::EncodingMask) >> 1194 X86II::EncodingShift; 1195 1196 // It uses the VEX.VVVV field? 1197 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 1198 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 1199 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 1200 const unsigned MemOp4_I8IMMOperand = 2; 1201 1202 // It uses the EVEX.aaa field? 1203 bool HasEVEX_K = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K); 1204 bool HasEVEX_RC = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_RC); 1205 1206 // Determine where the memory operand starts, if present. 1207 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode); 1208 if (MemoryOperand != -1) MemoryOperand += CurOp; 1209 1210 // Emit the lock opcode prefix as needed. 1211 if (TSFlags & X86II::LOCK) 1212 EmitByte(0xF0, CurByte, OS); 1213 1214 // Emit segment override opcode prefix as needed. 1215 if (MemoryOperand >= 0) 1216 EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg, 1217 MI, OS); 1218 1219 // Emit the repeat opcode prefix as needed. 1220 if (TSFlags & X86II::REP) 1221 EmitByte(0xF3, CurByte, OS); 1222 1223 // Emit the address size opcode prefix as needed. 1224 bool need_address_override; 1225 // The AdSize prefix is only for 32-bit and 64-bit modes. Hm, perhaps we 1226 // should introduce an AdSize16 bit instead of having seven special cases? 1227 if ((!is16BitMode(STI) && TSFlags & X86II::AdSize) || 1228 (is16BitMode(STI) && (MI.getOpcode() == X86::JECXZ_32 || 1229 MI.getOpcode() == X86::MOV8o8a || 1230 MI.getOpcode() == X86::MOV16o16a || 1231 MI.getOpcode() == X86::MOV32o32a || 1232 MI.getOpcode() == X86::MOV8ao8 || 1233 MI.getOpcode() == X86::MOV16ao16 || 1234 MI.getOpcode() == X86::MOV32ao32))) { 1235 need_address_override = true; 1236 } else if (MemoryOperand < 0) { 1237 need_address_override = false; 1238 } else if (is64BitMode(STI)) { 1239 assert(!Is16BitMemOperand(MI, MemoryOperand, STI)); 1240 need_address_override = Is32BitMemOperand(MI, MemoryOperand); 1241 } else if (is32BitMode(STI)) { 1242 assert(!Is64BitMemOperand(MI, MemoryOperand)); 1243 need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI); 1244 } else { 1245 assert(is16BitMode(STI)); 1246 assert(!Is64BitMemOperand(MI, MemoryOperand)); 1247 need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI); 1248 } 1249 1250 if (need_address_override) 1251 EmitByte(0x67, CurByte, OS); 1252 1253 if (Encoding == 0) 1254 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS); 1255 else 1256 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 1257 1258 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); 1259 1260 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1261 BaseOpcode = 0x0F; // Weird 3DNow! encoding. 1262 1263 unsigned SrcRegNum = 0; 1264 switch (TSFlags & X86II::FormMask) { 1265 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n"; 1266 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!"); 1267 case X86II::Pseudo: 1268 llvm_unreachable("Pseudo instruction shouldn't be emitted"); 1269 case X86II::RawFrmDstSrc: { 1270 unsigned siReg = MI.getOperand(1).getReg(); 1271 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || 1272 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || 1273 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && 1274 "SI and DI register sizes do not match"); 1275 // Emit segment override opcode prefix as needed (not for %ds). 1276 if (MI.getOperand(2).getReg() != X86::DS) 1277 EmitSegmentOverridePrefix(CurByte, 2, MI, OS); 1278 // Emit AdSize prefix as needed. 1279 if ((!is32BitMode(STI) && siReg == X86::ESI) || 1280 (is32BitMode(STI) && siReg == X86::SI)) 1281 EmitByte(0x67, CurByte, OS); 1282 CurOp += 3; // Consume operands. 1283 EmitByte(BaseOpcode, CurByte, OS); 1284 break; 1285 } 1286 case X86II::RawFrmSrc: { 1287 unsigned siReg = MI.getOperand(0).getReg(); 1288 // Emit segment override opcode prefix as needed (not for %ds). 1289 if (MI.getOperand(1).getReg() != X86::DS) 1290 EmitSegmentOverridePrefix(CurByte, 1, MI, OS); 1291 // Emit AdSize prefix as needed. 1292 if ((!is32BitMode(STI) && siReg == X86::ESI) || 1293 (is32BitMode(STI) && siReg == X86::SI)) 1294 EmitByte(0x67, CurByte, OS); 1295 CurOp += 2; // Consume operands. 1296 EmitByte(BaseOpcode, CurByte, OS); 1297 break; 1298 } 1299 case X86II::RawFrmDst: { 1300 unsigned siReg = MI.getOperand(0).getReg(); 1301 // Emit AdSize prefix as needed. 1302 if ((!is32BitMode(STI) && siReg == X86::EDI) || 1303 (is32BitMode(STI) && siReg == X86::DI)) 1304 EmitByte(0x67, CurByte, OS); 1305 ++CurOp; // Consume operand. 1306 EmitByte(BaseOpcode, CurByte, OS); 1307 break; 1308 } 1309 case X86II::RawFrm: 1310 EmitByte(BaseOpcode, CurByte, OS); 1311 break; 1312 case X86II::RawFrmMemOffs: 1313 // Emit segment override opcode prefix as needed. 1314 EmitSegmentOverridePrefix(CurByte, 1, MI, OS); 1315 EmitByte(BaseOpcode, CurByte, OS); 1316 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1317 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1318 CurByte, OS, Fixups); 1319 ++CurOp; // skip segment operand 1320 break; 1321 case X86II::RawFrmImm8: 1322 EmitByte(BaseOpcode, CurByte, OS); 1323 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1324 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1325 CurByte, OS, Fixups); 1326 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte, 1327 OS, Fixups); 1328 break; 1329 case X86II::RawFrmImm16: 1330 EmitByte(BaseOpcode, CurByte, OS); 1331 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1332 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1333 CurByte, OS, Fixups); 1334 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte, 1335 OS, Fixups); 1336 break; 1337 1338 case X86II::AddRegFrm: 1339 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); 1340 break; 1341 1342 case X86II::MRMDestReg: 1343 EmitByte(BaseOpcode, CurByte, OS); 1344 SrcRegNum = CurOp + 1; 1345 1346 if (HasEVEX_K) // Skip writemask 1347 SrcRegNum++; 1348 1349 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1350 ++SrcRegNum; 1351 1352 EmitRegModRMByte(MI.getOperand(CurOp), 1353 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS); 1354 CurOp = SrcRegNum + 1; 1355 break; 1356 1357 case X86II::MRMDestMem: 1358 EmitByte(BaseOpcode, CurByte, OS); 1359 SrcRegNum = CurOp + X86::AddrNumOperands; 1360 1361 if (HasEVEX_K) // Skip writemask 1362 SrcRegNum++; 1363 1364 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1365 ++SrcRegNum; 1366 1367 EmitMemModRMByte(MI, CurOp, 1368 GetX86RegNum(MI.getOperand(SrcRegNum)), 1369 TSFlags, CurByte, OS, Fixups, STI); 1370 CurOp = SrcRegNum + 1; 1371 break; 1372 1373 case X86II::MRMSrcReg: 1374 EmitByte(BaseOpcode, CurByte, OS); 1375 SrcRegNum = CurOp + 1; 1376 1377 if (HasEVEX_K) // Skip writemask 1378 SrcRegNum++; 1379 1380 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1381 ++SrcRegNum; 1382 1383 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM) 1384 ++SrcRegNum; 1385 1386 EmitRegModRMByte(MI.getOperand(SrcRegNum), 1387 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1388 1389 // 2 operands skipped with HasMemOp4, compensate accordingly 1390 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1; 1391 if (HasVEX_4VOp3) 1392 ++CurOp; 1393 // do not count the rounding control operand 1394 if (HasEVEX_RC) 1395 NumOps--; 1396 break; 1397 1398 case X86II::MRMSrcMem: { 1399 int AddrOperands = X86::AddrNumOperands; 1400 unsigned FirstMemOp = CurOp+1; 1401 1402 if (HasEVEX_K) { // Skip writemask 1403 ++AddrOperands; 1404 ++FirstMemOp; 1405 } 1406 1407 if (HasVEX_4V) { 1408 ++AddrOperands; 1409 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1410 } 1411 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 1412 ++FirstMemOp; 1413 1414 EmitByte(BaseOpcode, CurByte, OS); 1415 1416 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), 1417 TSFlags, CurByte, OS, Fixups, STI); 1418 CurOp += AddrOperands + 1; 1419 if (HasVEX_4VOp3) 1420 ++CurOp; 1421 break; 1422 } 1423 1424 case X86II::MRMXr: 1425 case X86II::MRM0r: case X86II::MRM1r: 1426 case X86II::MRM2r: case X86II::MRM3r: 1427 case X86II::MRM4r: case X86II::MRM5r: 1428 case X86II::MRM6r: case X86II::MRM7r: { 1429 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1430 ++CurOp; 1431 if (HasEVEX_K) // Skip writemask 1432 ++CurOp; 1433 EmitByte(BaseOpcode, CurByte, OS); 1434 uint64_t Form = TSFlags & X86II::FormMask; 1435 EmitRegModRMByte(MI.getOperand(CurOp++), 1436 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r, 1437 CurByte, OS); 1438 break; 1439 } 1440 1441 case X86II::MRMXm: 1442 case X86II::MRM0m: case X86II::MRM1m: 1443 case X86II::MRM2m: case X86II::MRM3m: 1444 case X86II::MRM4m: case X86II::MRM5m: 1445 case X86II::MRM6m: case X86II::MRM7m: { 1446 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1447 ++CurOp; 1448 if (HasEVEX_K) // Skip writemask 1449 ++CurOp; 1450 EmitByte(BaseOpcode, CurByte, OS); 1451 uint64_t Form = TSFlags & X86II::FormMask; 1452 EmitMemModRMByte(MI, CurOp, (Form == X86II::MRMXm) ? 0 : Form-X86II::MRM0m, 1453 TSFlags, CurByte, OS, Fixups, STI); 1454 CurOp += X86::AddrNumOperands; 1455 break; 1456 } 1457 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: 1458 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8: 1459 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: 1460 case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4: 1461 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8: 1462 case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB: 1463 case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE: 1464 case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1: 1465 case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4: 1466 case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9: 1467 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: 1468 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0: 1469 case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3: 1470 case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6: 1471 case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9: 1472 case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC: 1473 case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF: 1474 EmitByte(BaseOpcode, CurByte, OS); 1475 1476 unsigned char MRM; 1477 switch (TSFlags & X86II::FormMask) { 1478 default: llvm_unreachable("Invalid Form"); 1479 case X86II::MRM_C0: MRM = 0xC0; break; 1480 case X86II::MRM_C1: MRM = 0xC1; break; 1481 case X86II::MRM_C2: MRM = 0xC2; break; 1482 case X86II::MRM_C3: MRM = 0xC3; break; 1483 case X86II::MRM_C4: MRM = 0xC4; break; 1484 case X86II::MRM_C8: MRM = 0xC8; break; 1485 case X86II::MRM_C9: MRM = 0xC9; break; 1486 case X86II::MRM_CA: MRM = 0xCA; break; 1487 case X86II::MRM_CB: MRM = 0xCB; break; 1488 case X86II::MRM_D0: MRM = 0xD0; break; 1489 case X86II::MRM_D1: MRM = 0xD1; break; 1490 case X86II::MRM_D4: MRM = 0xD4; break; 1491 case X86II::MRM_D5: MRM = 0xD5; break; 1492 case X86II::MRM_D6: MRM = 0xD6; break; 1493 case X86II::MRM_D8: MRM = 0xD8; break; 1494 case X86II::MRM_D9: MRM = 0xD9; break; 1495 case X86II::MRM_DA: MRM = 0xDA; break; 1496 case X86II::MRM_DB: MRM = 0xDB; break; 1497 case X86II::MRM_DC: MRM = 0xDC; break; 1498 case X86II::MRM_DD: MRM = 0xDD; break; 1499 case X86II::MRM_DE: MRM = 0xDE; break; 1500 case X86II::MRM_DF: MRM = 0xDF; break; 1501 case X86II::MRM_E0: MRM = 0xE0; break; 1502 case X86II::MRM_E1: MRM = 0xE1; break; 1503 case X86II::MRM_E2: MRM = 0xE2; break; 1504 case X86II::MRM_E3: MRM = 0xE3; break; 1505 case X86II::MRM_E4: MRM = 0xE4; break; 1506 case X86II::MRM_E5: MRM = 0xE5; break; 1507 case X86II::MRM_E8: MRM = 0xE8; break; 1508 case X86II::MRM_E9: MRM = 0xE9; break; 1509 case X86II::MRM_EA: MRM = 0xEA; break; 1510 case X86II::MRM_EB: MRM = 0xEB; break; 1511 case X86II::MRM_EC: MRM = 0xEC; break; 1512 case X86II::MRM_ED: MRM = 0xED; break; 1513 case X86II::MRM_EE: MRM = 0xEE; break; 1514 case X86II::MRM_F0: MRM = 0xF0; break; 1515 case X86II::MRM_F1: MRM = 0xF1; break; 1516 case X86II::MRM_F2: MRM = 0xF2; break; 1517 case X86II::MRM_F3: MRM = 0xF3; break; 1518 case X86II::MRM_F4: MRM = 0xF4; break; 1519 case X86II::MRM_F5: MRM = 0xF5; break; 1520 case X86II::MRM_F6: MRM = 0xF6; break; 1521 case X86II::MRM_F7: MRM = 0xF7; break; 1522 case X86II::MRM_F8: MRM = 0xF8; break; 1523 case X86II::MRM_F9: MRM = 0xF9; break; 1524 case X86II::MRM_FA: MRM = 0xFA; break; 1525 case X86II::MRM_FB: MRM = 0xFB; break; 1526 case X86II::MRM_FC: MRM = 0xFC; break; 1527 case X86II::MRM_FD: MRM = 0xFD; break; 1528 case X86II::MRM_FE: MRM = 0xFE; break; 1529 case X86II::MRM_FF: MRM = 0xFF; break; 1530 } 1531 EmitByte(MRM, CurByte, OS); 1532 break; 1533 } 1534 1535 // If there is a remaining operand, it must be a trailing immediate. Emit it 1536 // according to the right size for the instruction. Some instructions 1537 // (SSE4a extrq and insertq) have two trailing immediates. 1538 while (CurOp != NumOps && NumOps - CurOp <= 2) { 1539 // The last source register of a 4 operand instruction in AVX is encoded 1540 // in bits[7:4] of a immediate byte. 1541 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { 1542 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand 1543 : CurOp); 1544 ++CurOp; 1545 unsigned RegNum = GetX86RegNum(MO) << 4; 1546 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1547 RegNum |= 1 << 7; 1548 // If there is an additional 5th operand it must be an immediate, which 1549 // is encoded in bits[3:0] 1550 if (CurOp != NumOps) { 1551 const MCOperand &MIMM = MI.getOperand(CurOp++); 1552 if (MIMM.isImm()) { 1553 unsigned Val = MIMM.getImm(); 1554 assert(Val < 16 && "Immediate operand value out of range"); 1555 RegNum |= Val; 1556 } 1557 } 1558 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, 1559 CurByte, OS, Fixups); 1560 } else { 1561 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1562 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1563 CurByte, OS, Fixups); 1564 } 1565 } 1566 1567 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1568 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); 1569 1570 #ifndef NDEBUG 1571 // FIXME: Verify. 1572 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { 1573 errs() << "Cannot encode all operands of: "; 1574 MI.dump(); 1575 errs() << '\n'; 1576 abort(); 1577 } 1578 #endif 1579 } 1580