| /external/pcre/dist/sljit/ |
| sljitNativeMIPS_64.c | 38 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
45 return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SLJIT_SUCCESS;
81 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 32), dst_ar));
89 return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar);
114 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 48), dst_ar));
118 return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar);
234 FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM((op & SLJIT_INT_OP) ? 32 : 64), UNMOVABLE_INS));
257 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(ULESS_FLAG) | IMM(src2), ULESS_FLAG));
293 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OVERFLOW_FLAG) | IMM(src2), OVERFLOW_FLAG));
415 EMIT_LOGICAL(ORI, OR)
[all...] |
| sljitNativePPC_64.c | 55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
59 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS;
77 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp >> 32)));
89 return push_inst(compiler, ORI | S(reg) | A(reg) | tmp2);
96 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp2)) : SLJIT_SUCCESS;
107 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | (tmp2 >> 48)));
113 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm >> 32)));
116 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm));
312 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm);
320 FAIL_IF(push_inst(compiler, ORI | S(src1) | A(dst) | IMM(compiler->imm)))
[all...] |
| sljitNativePPC_32.c | 35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS;
185 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm);
193 FAIL_IF(push_inst(compiler, ORI | S(src1) | A(dst) | IMM(compiler->imm)));
250 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(init_value));
|
| sljitNativeMIPS_32.c | 32 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
38 return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SLJIT_SUCCESS;
142 FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM(32), UNMOVABLE_INS));
165 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(ULESS_FLAG) | IMM(src2), ULESS_FLAG));
201 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OVERFLOW_FLAG) | IMM(src2), OVERFLOW_FLAG));
320 EMIT_LOGICAL(ORI, OR);
347 return push_inst(compiler, ORI | S(dst) | T(dst) | IMM(init_value), DR(dst));
|
| sljitNativeTILEGX_64.c | 426 #define ORI(dst, srca, imm) \
[all...] |
| /external/valgrind/main/none/tests/mips64/ |
| logical_instructions.c | 7 OR, ORI, XOR, XORI
68 case ORI:
70 TEST2("ori $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
71 TEST2("ori $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
72 TEST2("ori $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
73 TEST2("ori $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
74 TEST2("ori $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1);
75 TEST2("ori $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
76 TEST2("ori $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
77 TEST2("ori $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1)
[all...] |
| /external/chromium_org/v8/src/mips/ |
| constants-mips.cc | 302 case ORI:
|
| assembler-mips-inl.h | 149 // For an instruction like LUI/ORI where the target bits are mixed into the
357 (instr1 & kOpcodeMask) == ORI &&
|
| assembler-mips.cc | 205 // specially coded on MIPS means that it is a lui/ori instruction, and that is
582 return opcode == ORI;
1574 void Assembler::ori(Register rt, Register rs, int32_t j) { function in class:v8::Assembler
[all...] |
| constants-mips.h | 329 ORI = ((1 << 3) + 5) << kOpcodeShift,
|
| simulator-mips.cc | [all...] |
| macro-assembler-mips.cc | 848 ori(rd, rs, rt.imm32_);
1002 ori(rd, zero_reg, j.imm32_);
1007 ori(rd, rd, (j.imm32_ & kImm16Mask));
1016 ori(rd, rd, (j.imm32_ & kImm16Mask));
[all...] |
| /external/chromium_org/v8/src/mips64/ |
| constants-mips64.cc | 320 case ORI:
|
| assembler-mips64-inl.h | 141 // For an instruction like LUI/ORI where the target bits are mixed into the
348 Instr instr1 = Assembler::instr_at(pc_ + 1 * Assembler::kInstrSize); // ori.
350 Instr instr3 = Assembler::instr_at(pc_ + 3 * Assembler::kInstrSize); // ori.
354 (instr1 & kOpcodeMask) == ORI &&
356 (instr3 & kOpcodeMask) == ORI &&
|
| assembler-mips64.cc | 183 // specially coded on MIPS means that it is a lui/ori instruction, and that is
554 return opcode == ORI;
1638 void Assembler::ori(Register rt, Register rs, int32_t j) { function in class:v8::Assembler
[all...] |
| constants-mips64.h | 294 ORI = ((1 << 3) + 5) << kOpcodeShift,
|
| macro-assembler-mips64.cc | 925 ori(rd, rs, rt.imm64_);
1112 ori(rd, zero_reg, (j.imm64_ & kImm16Mask));
1117 ori(rd, rd, (j.imm64_ & kImm16Mask));
1121 ori(rd, rd, (j.imm64_ >> 32) & kImm16Mask);
1123 ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask);
1125 ori(rd, rd, j.imm64_ & kImm16Mask);
1130 ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask);
1132 ori(rd, rd, j.imm64_ & kImm16Mask);
1137 ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask);
1139 ori(rd, rd, j.imm64_ & kImm16Mask)
[all...] |
| simulator-mips64.cc | [all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 387 mMips->ORI(tmpReg, tmpReg, (amode.value & 0x0000ffff));
471 mMips->ORI(Rd, Rn, src);
478 mMips->ORI(R_at, 0, src);
488 mMips->ORI(R_at, 0, src);
501 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
504 mMips->ORI(Rd, 0, amode.value);
533 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
536 mMips->ORI(Rd, 0, amode.value);
579 mMips->ORI(R_cmp2, R_zero, src);
[all...] |
| MIPSAssembler.h | 307 void ORI(int Rt, int Rs, uint16_t imm);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 254 // transform this into the appropriate ORI instruction.
303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
566 : PPC::ORI );
863 : PPC::ORI );
[all...] |
| PPCFastISel.cpp | [all...] |
| PPCRegisterInfo.cpp | 806 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
[all...] |
| /external/chromium_org/third_party/icu/source/common/ |
| ucnvisci.c | 92 ORI = 0x47,
145 { ORIYA, ORI_MASK, ORI },
273 * | DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML |
[all...] |
| /external/icu/icu4c/source/common/ |
| ucnvisci.c | 92 ORI = 0x47,
145 { ORIYA, ORI_MASK, ORI },
273 * | DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML |
[all...] |
