| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 123 int Rd, int Rn,
128 int Rd, int Rm, int Rs, int Rn) = 0;
143 virtual void BX(int cc, int Rn) = 0;
154 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
156 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
158 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
160 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
163 int Rn, uint32_t offset = __immed8_pre(0)) = 0;
165 int Rn, uint32_t offset = __immed8_pre(0)) = 0;
167 int Rn, uint32_t offset = __immed8_pre(0)) = 0
[all...] |
| ARMAssemblerInterface.cpp | 69 int Rn, uint32_t offset)
71 LDR(cc, Rd, Rn, offset);
74 int Rn, uint32_t offset)
76 STR(cc, Rd, Rn, offset);
79 int Rd, int Rn, uint32_t Op2)
81 dataProcessing(opADD, cc, s, Rd, Rn, Op2);
84 int Rd, int Rn, uint32_t Op2)
86 dataProcessing(opSUB, cc, s, Rd, Rn, Op2);
|
| Arm64Assembler.cpp | 341 int s, int Rd, int Rn, uint32_t Op2)
398 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
399 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
400 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
401 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
402 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
409 int s, int Rd, int Rn, uint32_t Op2)
420 dataProcessingCommon(opcode, s, Wd, Rn, Op2);
424 dataProcessingCommon(opSUB, 1, mTmpReg3, Rn, Op2);
428 dataProcessingCommon(opSUB, s, Wd, Rn, Op2)
[all...] |
| ARMAssemblerProxy.cpp | 161 int Rd, int Rn, uint32_t Op2)
163 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2);
166 void ARMAssemblerProxy::MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) {
167 mTarget->MLA(cc, s, Rd, Rm, Rs, Rn);
195 void ARMAssemblerProxy::BX(int cc, int Rn) {
196 mTarget->BX(cc, Rn);
212 void ARMAssemblerProxy::LDR(int cc, int Rd, int Rn, uint32_t offset) {
213 mTarget->LDR(cc, Rd, Rn, offset);
215 void ARMAssemblerProxy::LDRB(int cc, int Rd, int Rn, uint32_t offset) {
216 mTarget->LDRB(cc, Rd, Rn, offset)
[all...] |
| Arm64Assembler.h | 99 int Rd, int Rn,
102 int Rd, int Rm, int Rs, int Rn);
116 virtual void BX(int cc, int Rn);
124 int Rn, uint32_t offset = 0);
126 int Rn, uint32_t Op2);
128 int Rn, uint32_t Op2);
130 int Rn, uint32_t offset = 0);
133 int Rn, uint32_t offset = 0);
135 int Rn, uint32_t offset = 0);
137 int Rn, uint32_t offset = 0)
[all...] |
| ARMAssemblerProxy.h | 80 int Rd, int Rn,
83 int Rd, int Rm, int Rs, int Rn);
97 virtual void BX(int cc, int Rn);
105 int Rn, uint32_t offset = __immed12_pre(0));
107 int Rn, uint32_t offset = __immed12_pre(0));
109 int Rn, uint32_t offset = __immed12_pre(0));
111 int Rn, uint32_t offset = __immed12_pre(0));
113 int Rn, uint32_t offset = __immed8_pre(0));
115 int Rn, uint32_t offset = __immed8_pre(0));
117 int Rn, uint32_t offset = __immed8_pre(0))
[all...] |
| ARMAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
108 virtual void BX(int cc, int Rn);
116 int Rn, uint32_t offset = __immed12_pre(0));
118 int Rn, uint32_t offset = __immed12_pre(0));
120 int Rn, uint32_t offset = __immed12_pre(0));
122 int Rn, uint32_t offset = __immed12_pre(0));
124 int Rn, uint32_t offset = __immed8_pre(0));
126 int Rn, uint32_t offset = __immed8_pre(0));
128 int Rn, uint32_t offset = __immed8_pre(0))
[all...] |
| ARMAssembler.cpp | 217 int s, int Rd, int Rn, uint32_t Op2)
219 *mPC++ = (cc<<28) | (opcode<<21) | (s<<20) | (Rn<<16) | (Rd<<12) | Op2;
229 int Rd, int Rm, int Rs, int Rn) {
231 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
233 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
288 void ARMAssembler::BX(int cc, int Rn)
290 *mPC++ = (cc<<28) | 0x12FFF10 | Rn;
299 void ARMAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset) {
300 *mPC++ = (cc<<28) | (1<<26) | (1<<20) | (Rn<<16) | (Rd<<12) | offset;
302 void ARMAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
[all...] |
| MIPSAssembler.cpp | 418 int s, int Rd, int Rn, uint32_t Op2)
435 mMips->AND(Rd, Rn, src);
437 mMips->ANDI(Rd, Rn, src);
444 mMips->ADDU(Rd, Rn, src);
446 mMips->ADDIU(Rd, Rn, src);
453 mMips->SUBU(Rd, Rn, src);
455 mMips->SUBIU(Rd, Rn, src);
461 mMips->XOR(Rd, Rn, src);
463 mMips->XORI(Rd, Rn, src);
469 mMips->OR(Rd, Rn, src)
[all...] |
| MIPSAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
108 virtual void BX(int cc, int Rn);
116 int Rn, uint32_t offset = 0);
118 int Rn, uint32_t offset = 0);
120 int Rn, uint32_t offset = 0);
122 int Rn, uint32_t offset = 0);
124 int Rn, uint32_t offset = 0);
126 int Rn, uint32_t offset = 0);
128 int Rn, uint32_t offset = 0)
[all...] |
| /art/disassembler/ |
| disassembler_arm.cc | 311 ArmRegister rn(instruction, 16);
312 if (rn.r == 0xf) {
318 args << "[" << rn << ", #" << offset << "]";
320 args << "[" << rn << ", #" << offset << "]!";
322 args << "[" << rn << "], #" << offset;
326 if (rn.r == 9) {
467 // |111|01|00|op|0|WL| Rn | |
476 ArmRegister Rn(instr, 16);
481 args << Rn << (W == 0 ? "" : "!") << ", ";
483 if (Rn.r != 13)
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/lldb/source/Plugins/Instruction/ARM/ |
| EmulateInstructionARM.cpp | 943 // d = UInt(Rdm); n = UInt(Rn); m = UInt(Rdm); setflags = !InITBlock();
956 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
969 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
[all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 415 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3)
429 regs[Rn] = test.RnValue;
450 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
451 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
452 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break;
453 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break;
454 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break;
455 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break;
457 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
458 case INSTR_CMP: a64asm->CMP(test.cond, Rn,op2); break
[all...] |
| /external/vixl/src/a64/ |
| assembler-a64.cc | 433 Emit(BR | Rn(xn));
439 Emit(BLR | Rn(xn));
445 Emit(RET | Rn(xn));
545 const Register& rn,
547 AddSub(rd, rn, operand, LeaveFlags, ADD);
552 const Register& rn,
554 AddSub(rd, rn, operand, SetFlags, ADD);
558 void Assembler::cmn(const Register& rn,
560 Register zr = AppropriateZeroRegFor(rn);
561 adds(zr, rn, operand)
654 ands(AppropriateZeroRegFor(rn), rn, operand); local
[all...] |
| disasm-a64.h | 74 return (instr->Rn() == kZeroRegCode);
|
| simulator-a64.cc | 543 Instruction* target = Instruction::Cast(xreg(instr->Rn()));
599 reg(reg_size, instr->Rn(), instr->RnMode()),
607 reg(reg_size, instr->Rn(), instr->RnMode()),
656 reg(reg_size, instr->Rn()),
684 int64_t op1 = reg(reg_size, instr->Rn());
723 int64_t op1 = reg(reg_size, instr->Rn());
777 uint8_t* address = AddressModeHelper(instr->Rn(), offset, addrmode);
844 uint8_t* address = AddressModeHelper(instr->Rn(), offset, addrmode);
1059 uint64_t new_val = xreg(instr->Rn());
1082 unsigned src = instr->Rn();
1150 int32_t rn = wreg(instr->Rn()); local
1163 int64_t rn = xreg(instr->Rn()); local
1176 uint32_t rn = static_cast<uint32_t>(wreg(instr->Rn())); local
1187 uint64_t rn = static_cast<uint64_t>(xreg(instr->Rn())); local
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 670 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
675 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
678 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| disasm-arm64.h | 55 return (instr->Rn() == kZeroRegCode);
|
| assembler-arm64.cc | 899 instr->following()->Rn() == xzr.code()));
935 Emit(BLR | Rn(xzr));
956 Emit(BR | Rn(xn));
966 Emit(BLR | Rn(xn));
973 Emit(RET | Rn(xn));
1194 ands(AppropriateZeroRegFor(rn), rn, operand); local
[all...] |
| simulator-arm64.cc | 883 reg<T>(instr->Rn()),
958 T op1 = reg<T>(instr->Rn());
2011 T rn = reg<T>(instr->Rn()); local
2026 unsignedT rn = static_cast<unsignedT>(reg<T>(instr->Rn())); local
[all...] |
| instrument-arm64.cc | 246 (instr->Rd() == 31) && (instr->Rn() == 31)) {
459 (instr->Rd() == 31) && (instr->Rn() == 31)) {
|
| disasm-arm64.cc | 101 const char *form = "'Rd, 'Rn, 'Rm'HDP";
102 const char *form_cmp = "'Rn, 'Rm'HDP";
185 const char *form = "'Rd, 'Rn, 'Rm";
221 const char *form = "'Rds, 'Rn, 'ITri";
250 form = "'Rn, 'ITri";
293 const char *form = "'Rd, 'Rn, 'Rm'HLo";
311 form = "'Rn, 'Rm'HLo";
342 const char *form = "'Rn, 'Rm, 'INzcv, 'Cond";
357 const char *form = "'Rn, 'IP, 'INzcv, 'Cond";
372 bool rn_is_rm = (instr->Rn() == instr->Rm())
[all...] |
| /external/chromium_org/v8/src/arm/ |
| disasm-arm.cc | 91 void FormatNeonMemory(int Rn, int align, int Rm);
303 if (format[1] == 'n') { // 'rn: Rn register
416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) {
418 "[r%d", Rn);
712 // Rn field to encode it.
713 Format(instr, "mul'cond's 'rn, 'rm, 'rs");
717 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
718 // Rn field to encode the Rd register and the Rd field to encode
719 // the Rn register
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | [all...] |
